[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp/cpx: enable PLATFORM_USES_FSP2_2

[Jonathan Zhang (Code Review)]

Hello Philipp Deppenwiese, build bot (Jenkins), Anjaneya "Reddy" Chagam, Patrick Georgi, Martin Roth, nateman1352, Angel Pons, Subrata Banik, Patrick Rudolph, Nate DeSimone,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44049

to look at the new patch set (#2).

Change subject: soc/intel/xeon_sp/cpx: enable PLATFORM_USES_FSP2_2
......................................................................

soc/intel/xeon_sp/cpx: enable PLATFORM_USES_FSP2_2

CPX-SP FSP is FSP 2.2, so select PLATFORM_USES_FSP2_2.

The workaround of hardcoding StackBase and StackSize FSP-M UPD
parameters is removed.

Add CPX-SP soc implementation of soc_fsp_multi_phase_init_is_enable()
to indicate that FSP-S multi phase init is not enabled, since it is
not supported by CPX-SP FSP.

Increase FSP_TEMP_RAM_SIZE, DCACHE_BSP_STACK_SIZE, and adjust
DCACHE_RAM_SIZE accordingly.

Correct DCACHE_RAM_BASE.

Remove duplicate entries in soc/intel/xeon_sp/cpx/Kconfig which
have same values as in soc/intel/xeon_sp/Kconfig.

Signed-off-by: Jonathan Zhang 
Change-Id: I25e39083df1ebfe78871561b0a0e230b66524ea9
---
M src/soc/intel/xeon_sp/Kconfig
M src/soc/intel/xeon_sp/cpx/Kconfig
M src/soc/intel/xeon_sp/cpx/Makefile.inc
A src/soc/intel/xeon_sp/cpx/ramstage.c
M src/soc/intel/xeon_sp/cpx/romstage.c
5 files changed, 21 insertions(+), 34 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/44049/2