[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Fix 16-bit read/write PCI_COMMAND register

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40844 )

Change subject: soc/intel/cannonlake: Fix 16-bit read/write PCI_COMMAND register
......................................................................

soc/intel/cannonlake: Fix 16-bit read/write PCI_COMMAND register

Change-Id: If7e2c84c39039e0dc6811f247390f856fc634b33
Signed-off-by: Elyes HAOUAS 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40844
Tested-by: build bot (Jenkins) 
Reviewed-by: Patrick Georgi 
---
M src/soc/intel/cannonlake/bootblock/pch.c
M src/soc/intel/cannonlake/graphics.c
2 files changed, 7 insertions(+), 9 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Georgi: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index d67edea..516359d 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -61,22 +61,21 @@
 static void soc_config_pwrmbase(void)
 {
    uint32_t reg32;
+	uint16_t reg16;

/*
     * Assign Resources to PWRMBASE
     * Clear BIT 1-2  Command Register
     */
-	reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
-	reg32 &= ~(PCI_COMMAND_MEMORY);
-	pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
+	reg16 = pci_read_config16(PCH_DEV_PMC, PCI_COMMAND);
+	reg16 &= ~(PCI_COMMAND_MEMORY);
+	pci_write_config16(PCH_DEV_PMC, PCI_COMMAND, reg16);

/* Program PWRM Base */
    pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);

/* Enable Bus Master and MMIO Space */
-	reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MEMORY;
-	pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
+	pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, PCI_COMMAND_MEMORY);

/* Enable PWRM in PMC */
    reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL));
diff --git a/src/soc/intel/cannonlake/graphics.c b/src/soc/intel/cannonlake/graphics.c
index c2f9957..1ecbb67 100644
--- a/src/soc/intel/cannonlake/graphics.c
+++ b/src/soc/intel/cannonlake/graphics.c
@@ -48,9 +48,8 @@
    }

/* IGD needs to Bus Master */
-	uint32_t reg32 = pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
-	pci_write_config32(dev, PCI_COMMAND, reg32);
+	pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
+			PCI_COMMAND_IO);

/*
     * GFX PEIM module inside FSP binary is taking care of graphics