[coreboot-gerrit] Change in coreboot[master]: mb/tigerlake: Disable Precision Time Measurement for PCIe RP 9

[Shreesh Chhabbi (Code Review)]

Hello Shreesh Chhabbi,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/44431

to review the following change.

Change subject: mb/tigerlake: Disable Precision Time Measurement for PCIe RP 9
......................................................................

mb/tigerlake: Disable Precision Time Measurement for PCIe RP 9

Change-Id: I72126c2013c4ddac2884b7d40ef043e80d432331
Signed-off-by: Shreesh Chhabbi 
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params.c
4 files changed, 10 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/44431/1

diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index b4a121a..9ccc5e0 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -63,6 +63,9 @@
    register "PcieClkSrcUsage[2]" = "0x3"
    register "PcieClkSrcUsage[3]" = "0x8"

+	# PCIe RP PTM
+	register "PciePtm[8]" = "0x0";
+
    register "SataSalpSupport" = "1"
    register "SataPortsEnable[0]" = "1"
    register "SataPortsEnable[1]" = "1"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index b08cd3c..496f837 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -52,6 +52,9 @@
    register "PcieRpLtrEnable[8]" = "1"
    register "PcieRpLtrEnable[10]" = "1"

+	# PCIe PTM for Root Port 9
+	register "PciePtm[8]" = "0"
+
    # Hybrid storage mode
    register "HybridStorageMode" = "1"

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 812dbac..3cadcf0 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -174,6 +174,9 @@
    /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
    uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];

+	/* PCIe Precision Time Measurement for Root Ports */
+	uint8_t PciePtm[CONFIG_MAX_ROOT_PORTS];
+
    /* PCIe RP L1 substate */
    enum L1_substates_control {
    	L1_SS_FSP_DEFAULT,
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 885a6f9..8a72573 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -172,6 +172,7 @@
    	params->PcieRpAdvancedErrorReporting[i] =
    		config->PcieRpAdvancedErrorReporting[i];
    	params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i];
+		params->PciePtm[i] = config->PciePtm[i];
    }

/* Enable ClkReqDetect for enabled port */