Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45056 )
Change subject: soc/amd/picasso: Add MADT entry for GNB IOAPIC ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45056/6/src/soc/amd/picasso/acpi.c File src/soc/amd/picasso/acpi.c:
https://review.coreboot.org/c/coreboot/+/45056/6/src/soc/amd/picasso/acpi.c@... PS6, Line 50: populates this
To Marshall's comment - is there any power implication by keeping it on all the time? I'm assuming n […]
Eric, I have a question in re. power. I assume it's negligible.
https://review.coreboot.org/c/coreboot/+/45056/6/src/soc/amd/picasso/acpi.c@... PS6, Line 50: FSP populates this generates this HOB if it initializes second IOAPIC I'd be fine with passing the address in and forcing FSP to obey the UPD. In that case, I'd probably take FSP's default back to disabled and make coreboot enable it intentionally.
Also, probably we want to also declare it as reserved resource here: https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/amd/common/block/...
Hmm, I thought we were already reserving a big chunk of space that should've covered it. Maybe I'm thinking of how Stoney Ridge though. You wouldn't put it in picasso/root_complex.c?