Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44706 )
Change subject: soc/mediatek/mt8192: Do dramc pre-settings before calibration ......................................................................
Patch Set 44:
(4 comments)
https://review.coreboot.org/c/coreboot/+/44706/44/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_basic_api.c:
https://review.coreboot.org/c/coreboot/+/44706/44/src/soc/mediatek/mt8192/dr... PS44, Line 116: case 0: : write_latency = 4; : break; : case 1: : write_latency = 6; : break; : case 2: : write_latency = 8; : break; : case 3: : write_latency = 10; : break; : case 4: : write_latency = 12; : break; : case 5: : write_latency = 14; : break; : case 6: : write_latency = 16; : break; : case 7: : write_latency = 18; : break;
Is the following the right logic? […]
The values are from JEDEC LPDDR4 spec. " For x16 mode WL Set "A” (MR2 OP[6]=0B) 000B: WL=4 (Default) 001B: WL=6 010B: WL=8 011B: WL=10 100B: WL=12 101B: WL=14 110B: WL=16 111B: WL=18 " Your formula result is right, but the SPEC doesn't mean that it's calculated by mr_wl * 2 + 4, so can we just follow the spec literal settings?
https://review.coreboot.org/c/coreboot/+/44706/44/src/soc/mediatek/mt8192/dr... PS44, Line 157: small_ui_to_large
Can we name it 'shift'?
Ack
https://review.coreboot.org/c/coreboot/+/44706/44/src/soc/mediatek/mt8192/dr... PS44, Line 167: (
No parentheses.
Ack
https://review.coreboot.org/c/coreboot/+/44706/44/src/soc/mediatek/mt8192/dr... PS44, Line 170: (
No parentheses.
Ack