[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Update FSP params for Jasper Lake

[Rizwan Qureshi (Code Review)]

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38461 )

Change subject: soc/intel/tigerlake: Update FSP params for Jasper Lake
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Patch Set 23:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38461/23/src/soc/intel/tigerlake/in... 
File src/soc/intel/tigerlake/include/soc/pci_devs.h:

https://review.coreboot.org/c/coreboot/+/38461/23/src/soc/intel/tigerlake/in... 
PS23, Line 90: XHCI
This is confusing, why XHCI?