[coreboot-gerrit] [S] Change in coreboot[master]: soc/amd/common/block/lpc'lpc: simplify index handling in read resources

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger.

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74849 )

Change subject: soc/amd/common/block/lpc'lpc: simplify index handling in read resources
......................................................................

soc/amd/common/block/lpc'lpc: simplify index handling in read resources

Now that we don't need to find a specific resource in the set resources
function any more, there's no need to use hard-coded indices for the
fixed resources. Instead use an index variable that gets incremented
after each fixed resource got added. The index now starts at 0 instead
of at 1, but now the only requirement is that those indices are unique.

Signed-off-by: Felix Held 
Change-Id: Ida5f1f001c622da2e31474b62832782f5f303a32
---
M src/soc/amd/common/block/lpc/lpc.c
1 file changed, 22 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/74849/1

diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c
index 79a1d59..3d5775f 100644
--- a/src/soc/amd/common/block/lpc/lpc.c
+++ b/src/soc/amd/common/block/lpc/lpc.c
@@ -106,6 +106,7 @@
 static void lpc_read_resources(struct device *dev)
 {
    struct resource *res;
+	unsigned long idx = 0;

/* Get the normal pci resources of this device */
    pci_dev_read_resources(dev);
@@ -118,20 +119,20 @@
    	     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;

/* Only up to 16 MByte of the SPI flash can be mapped right below 4 GB */
-	mmio_range(dev, 1, FLASH_BELOW_4GB_MAPPING_REGION_BASE,
+	mmio_range(dev, idx++, FLASH_BELOW_4GB_MAPPING_REGION_BASE,
    	   FLASH_BELOW_4GB_MAPPING_REGION_SIZE);

/* Add a memory resource for the SPI BAR. */
-	mmio_range(dev, 2, SPI_BASE_ADDRESS, 4 * KiB);
+	mmio_range(dev, idx++, SPI_BASE_ADDRESS, 4 * KiB);

/* Add a memory resource for the eSPI MMIO */
-	mmio_range(dev, 3, SPI_BASE_ADDRESS + ESPI_OFFSET_FROM_BAR, 4 * KiB);
+	mmio_range(dev, idx++, SPI_BASE_ADDRESS + ESPI_OFFSET_FROM_BAR, 4 * KiB);

/* FCH IOAPIC */
-	mmio_range(dev, 4, IO_APIC_ADDR, 4 * KiB);
+	mmio_range(dev, idx++, IO_APIC_ADDR, 4 * KiB);

/* HPET */
-	mmio_range(dev, 5, HPET_BASE_ADDRESS, 4 * KiB);
+	mmio_range(dev, idx++, HPET_BASE_ADDRESS, 4 * KiB);

compact_resources(dev);
 }