[coreboot-gerrit] [S] Change in coreboot[master]: [WIP] soc/amd: Change CPU ASL for p-states

[Kyösti Mälkki (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held.

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71614 )

Change subject: [WIP] soc/amd: Change CPU ASL for p-states
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Patch Set 1:

(1 comment)

File src/soc/amd/common/block/include/amdblocks/acpi.h:

https://review.coreboot.org/c/coreboot/+/71614/comment/a1cf15bb_c4b755b7 
PS1, Line 20: #define MMIO_ACPI_GPE0_BLK		0x14
> We have offsets 0x0c/0x14 here, 0x10/0x20 in IO space. […]

Found 55570-B1 Rev 3.16 - Apr 14, 2021

So MMIO and IO space maps cannot be symmetric.

The trap MSRC001_0073 [C-state Base Address] is for IO space, 8 consecutive addresses. And PMx66 has bits 0:2 marked reserved.

While offset 0x0c (80c) is defined in

9.1.10 FCH Register Access Information Guide

the detailed usage through MMIO is omitted from

9.2.10.4 Standard ACPI Registers