[coreboot-gerrit] Change in coreboot[master]: security/intel/txt: Fix variable MTRR handling

[Angel Pons (Code Review)]

Hello Philipp Deppenwiese, build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44183

to look at the new patch set (#3).

Change subject: security/intel/txt: Fix variable MTRR handling
......................................................................

security/intel/txt: Fix variable MTRR handling

The MSR macros were treated as memory addresses and the loops had
off-by-one errors. This resulted in a CPU exception before GETSEC, and
another exception after GETSEC (once the first exception was fixed).

Tested on Asrock B85M Pro4, ACM complains about the missing TPM and
resets the platform. When the `getsec` instruction is commented-out, the
board is able to boot normally, without any exceptions nor corruption.

Change-Id: Ib5d23cf9885401f3ec69b0f14cea7bad77eee19a
Signed-off-by: Angel Pons 
---
M src/security/intel/txt/getsec_enteraccs.S
1 file changed, 47 insertions(+), 48 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/44183/3