6 Oct
2020
6 Oct
'20
7:51 p.m.
Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44493 )
Change subject: commonlib/storage/mmc: Add DS and DDR50 speed modes ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44493/2/src/commonlib/storage/mmc.c File src/commonlib/storage/mmc.c:
https://review.coreboot.org/c/coreboot/+/44493/2/src/commonlib/storage/mmc.c... PS2, Line 197: Increase
Is it increasing, though?
Yes, initially "SDHCI bus clock: 0.097 MHz", then this changes to 25,50 or 200Mhz depending on the speed. I can change it to "Configure" if you think it is needed.
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Gerrit-Project: coreboot
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