[coreboot-gerrit] [XS] Change in coreboot[main]: soc/amd/glinda: Select SOC_FILL_CPU_CACHE_INFO

[Naresh Solanki (Code Review)]

Naresh Solanki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87222?usp=email )

Change subject: soc/amd/glinda: Select SOC_FILL_CPU_CACHE_INFO
......................................................................

soc/amd/glinda: Select SOC_FILL_CPU_CACHE_INFO

Use soc_fill_cpu_cache_info implementation to for computing L3 cache
size accurately for Glinda SoC.

Change-Id: I2827508ec0ae5f16d609e1bc76c00eb376a7b71b
Signed-off-by: Naresh Solanki 
---
M src/soc/amd/glinda/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/87222/1

diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index a02492c..1329108 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -81,6 +81,7 @@
    select SOC_AMD_COMMON_FSP_PCI			# TODO: Check if this is still correct
    select SOC_AMD_COMMON_FSP_PRELOAD_FSPS
    select SOC_AMD_COMMON_ROMSTAGE_LEGACY_DMA_FIXUP
+	select SOC_FILL_CPU_CACHE_INFO
    select SSE2
    select UDK_2017_BINDING
    select USE_DDR5