[coreboot-gerrit] Change in coreboot[master]: mb/gigabyte/ga-g41m-es2l: Add timestamps in romstage

[Arthur Heymans (Code Review)]

Arthur Heymans has submitted this change and it was merged. ( https://review.coreboot.org/19513 )

Change subject: mb/gigabyte/ga-g41m-es2l: Add timestamps in romstage
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mb/gigabyte/ga-g41m-es2l: Add timestamps in romstage

Change-Id: I93f43a0af41ae86f1b8ba33e28f3b9f060a5ab5e
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/19513
Tested-by: build bot (Jenkins) 
Reviewed-by: Philippe Mathieu-Daudé 
Reviewed-by: Martin Roth 
---
M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
1 file changed, 6 insertions(+), 0 deletions(-)

Approvals:
  Philippe Mathieu-Daudé: Looks good to me, but someone else must approve
  build bot (Jenkins): Verified
  Martin Roth: Looks good to me, approved

diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
index 229f028..b16f736 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
@@ -31,6 +31,7 @@
 #include <arch/stages.h>
 #include <cbmem.h>
 #include <northbridge/intel/x4x/iomap.h>
+#include <timestamp.h>

#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
 #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
@@ -135,6 +136,9 @@
    u8 boot_path = 0;
    u8 s3_resume;

+	timestamp_init(get_initial_timestamp());
+	timestamp_add_now(TS_START_ROMSTAGE);
+
    /* Disable watchdog timer */
    RCBA32(0x3410) = RCBA32(0x3410) | 0x20;

@@ -160,7 +164,9 @@
    	boot_path = BOOT_PATH_WARM_RESET;

printk(BIOS_DEBUG, "Initializing memory\n");
+	timestamp_add_now(TS_BEFORE_INITRAM);
    sdram_initialize(boot_path, spd_addrmap);
+	timestamp_add_now(TS_AFTER_INITRAM);
    quick_ram_check();
    printk(BIOS_DEBUG, "Memory initialized\n");