Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85821?usp=email )
Change subject: mb/asus/p8x7x-series: Drop unused MRC devicetree setting ......................................................................
mb/asus/p8x7x-series: Drop unused MRC devicetree setting
Drop MRC setting usb3.hs_port_switch_mask that since commit ee126348726b (nb/sandybridge,sb/bd82x6x: Configure USB from southbridge devicetree) mirrors xhci_switchable_ports and is no longer used separately.
Change-Id: Ic1937461ab45f74f29521a8692629290bfd3c560 Signed-off-by: Keith Hui buurin@gmail.com --- M src/mainboard/asus/p8x7x-series/devicetree.cb 1 file changed, 0 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/85821/1
diff --git a/src/mainboard/asus/p8x7x-series/devicetree.cb b/src/mainboard/asus/p8x7x-series/devicetree.cb index 979f124..e4e8d84 100644 --- a/src/mainboard/asus/p8x7x-series/devicetree.cb +++ b/src/mainboard/asus/p8x7x-series/devicetree.cb @@ -7,13 +7,6 @@ register "max_mem_clock_mhz" = "800" register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}"
- # 4 bit switch mask. 0=not switchable, 1=switchable - # Means once it's loaded the OS, it can swap ports - # from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf - register "usb3.hs_port_switch_mask" = "0xf" - # (The other 3 usb3.* settings can be set from nvram options, and so are set - # from runtime code) - device domain 0 on device ref peg10 on end # PCIEX16_1 device ref igd on end