Matt Papageorge has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42567 )
Change subject: soc/amd/picasso: Populate EFS SPI values ......................................................................
soc/amd/picasso: Populate EFS SPI values
The Embedded Firmware Structure should contain various SPI parameters for the PSP to program. This information is currently only programmed at run-time. This change is to also populate them at build time as well.
BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius.
Signed-off-by: Matt Papageorge matt.papageorge@amd.corp-partner.google.com Change-Id: I78558fa3fa27c70820f0f3d636544127adab6f8b --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc 2 files changed, 49 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/42567/1
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index dd5731d..963b329a 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -362,6 +362,39 @@ removes arbitration with board and assumes the chipset controls the SPI flash bus entirely.
+config EFS_SPI_READ_MODE + hex + default 0x2 + help + SPI Read Mode: + 000b Normal Read (up to 33M) + 001b Reserved + 010b Dual IO (1-1-2) + 011b Quad IO (1-1-4) + 100b Dual IO (1-2-2) + 101b Quad IO (1-4-4) + 110b Normal Read (up to 66M) + 111b Fast Read + +config EFS_SPI_SPEED + hex + default 0x0 + help + FastSpeedNew value: + 0000b 66.66Mhz + 0001b 33.33MHz + 0010b 22.22MHz + 0011b 16.66MHz + 0100b 100MHz + 0101b 800KHz + +config EFS_SPI_QUAD_DUMMY_CYCLE + hex + default 0xa + help + Dummy cycle configure. For SPI chips from Micron this value should + be 0x0A. Otherwise it should be 0xFF. + config MAINBOARD_POWER_RESTORE def_bool n help diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 796f77c..9dee50b 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -237,6 +237,13 @@ $(foreach bit,$(PSP_SOFTFUSE_BITS),$(call set-bit,$(bit)))); printf "0x%x" $$A)
# +# SOC family and model info +# +SOC_FAMILY=0x17 +SOC_MODEL_MIN=0x0 +SOC_MODEL_MAX=0x2f + +# # Build the arguments to amdfwtool (order is unimportant). Missing file names # result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool. # @@ -269,6 +276,9 @@ OPT_ABL5_FILE=$(call add_opt_prefix, $(PSP_ABL5_FILE), --abl-image) OPT_ABL6_FILE=$(call add_opt_prefix, $(PSP_ABL6_FILE), --abl-image) OPT_ABL7_FILE=$(call add_opt_prefix, $(PSP_ABL7_FILE), --abl-image) +OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode) +OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed) +OPT_EFS_SPI_QUAD_DUMMY_CYCLE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_QUAD_DUMMY_CYCLE), --spi-micron-flag) OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist)
OPT_PSP_APCB_FILES=$(foreach i, $(shell seq $(words $(PSP_APCB_FILES))), \ @@ -420,6 +430,12 @@ --combo-capable \ $(OPT_TOKEN_UNLOCK) \ --flashsize $(CONFIG_ROM_SIZE) \ + $(OPT_EFS_SPI_READ_MODE) \ + $(OPT_EFS_SPI_SPEED) \ + $(OPT_EFS_SPI_QUAD_DUMMY_CYCLE) \ + --soc-family $(SOC_FAMILY) \ + --soc-model-min $(SOC_MODEL_MIN) \ + --soc-model-max $(SOC_MODEL_MAX) \ --location $(shell printf "0x%x" $(PICASSO_FWM_POSITION)) \ --output $@