[coreboot-gerrit] Change in coreboot[master]: vendorcode/intel/fsp/fsp2_0/glk: Add nWR config in Odt Config

[Kane Chen (Code Review)]

Kane Chen has uploaded a new patch set (#2). ( https://review.coreboot.org/27814 )

Change subject: vendorcode/intel/fsp/fsp2_0/glk: Add nWR config in Odt Config
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vendorcode/intel/fsp/fsp2_0/glk: Add nWR config in Odt Config

From doc 571118, the bit 5 of OdtConfig is nWR config.
If the bit 5 is set, MRC will set MR1 nWR field to 24.
If the bit 5 is clear, MRC will set MR1 nWR field to 6.

Change-Id: Ic8e4e2ffb098c8ba2f670535981e9a30c3d45b64
Signed-off-by: Kane Chen 
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M src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/27814/2