Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40018 )
Change subject: sb/intel/bd82x6x/pcie.c: Replace ASSERT with check ......................................................................
sb/intel/bd82x6x/pcie.c: Replace ASSERT with check
The ASSERT statement includes a reference to the line number, which breaks timeless builds when the line it is on changes. To ease the verification of subsequent changes, use a regular check instead.
Change-Id: I605793e2ca9a956c18c3abc20192b158a7959210 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/bd82x6x/pcie.c 1 file changed, 1 insertion(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/40018/1
diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 84309a4..957d4e5 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -21,7 +21,6 @@ #include <device/pciexp.h> #include <device/pci_ids.h> #include <southbridge/intel/common/pciehp.h> -#include <assert.h>
#include "chip.h" #include "pch.h" @@ -289,9 +288,7 @@
static const char *pch_pcie_acpi_name(const struct device *dev) { - ASSERT(dev); - - if (PCI_SLOT(dev->path.pci.devfn) == 0x1c) { + if (dev && PCI_SLOT(dev->path.pci.devfn) == 0x1c) { static const char *names[] = { "RP01", "RP02", "RP03",