[coreboot-gerrit] Change in coreboot[master]: cpu/x86: Cache stages for RESET_VECTOR_IN_RAM

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38728 )

Change subject: cpu/x86: Cache stages for RESET_VECTOR_IN_RAM
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Patch Set 1:
> Patch Set 1:
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> @Aaron and @Arthur, curious what you think of this and the next one of "Set/get DRAM consumed by..." as opposed to trying to do a lot of it in soc//picasso.  BTW, I would really prefer to cache _before_ loading and not just before running the early stages, but this may be a reasonable intermediate step.

topic:"WIP_wb_cache_postcar" attempts to set up caching before loading anything into cbmem/TSEG (postcar+ramstage). A guess a similar/unified approach could be used for romstage in dram?