Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46262 )
Change subject: mb/google/volteer/variants: Enable RTD3 for the NVMe device ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46262/13/src/mainboard/google/volte... File src/mainboard/google/volteer/variants/delbin/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/46262/13/src/mainboard/google/volte... PS13, Line 155: register "clock_pin" = "0"
or a macro would be more descriptive, e.g. […]
I thought about adding an enum, but the reality is the limit is very SOC specific and it just maps to integers and I don't think rtd3 driver is the right place to define it. (I think we should eventually extract the PCIe UPDs into a common struct and define it there)
I left this one as 0 because although it is redundant it is making it clear that this maps to pin 0.