Saurabh Mishra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81875?usp=email )
Change subject: mb/intel/lnlrvp: Add LNL reference mainboard for LNLRVP-M ......................................................................
mb/intel/lnlrvp: Add LNL reference mainboard for LNLRVP-M
This adds an initial mainboard code for lnlrvp, Intel Lunarlake reference platform.
Change-Id: I0792daf72f328930d5476e7363db50340919256a Signed-off-by: Saurabh Mishra mishra.saurabh@intel.com --- A src/mainboard/intel/lnl_dev/Kconfig A src/mainboard/intel/lnl_dev/Kconfig.name A src/mainboard/intel/lnl_dev/Makefile.mk A src/mainboard/intel/lnl_dev/board_id.c A src/mainboard/intel/lnl_dev/board_info.txt A src/mainboard/intel/lnl_dev/bootblock.c A src/mainboard/intel/lnl_dev/chromeos.c A src/mainboard/intel/lnl_dev/dsdt.asl A src/mainboard/intel/lnl_dev/ec.c A src/mainboard/intel/lnl_dev/fw_config.c A src/mainboard/intel/lnl_dev/include/baseboard/board_id.h A src/mainboard/intel/lnl_dev/include/baseboard/ec.h A src/mainboard/intel/lnl_dev/include/baseboard/gpio.h A src/mainboard/intel/lnl_dev/include/baseboard/variants.h A src/mainboard/intel/lnl_dev/mainboard.c A src/mainboard/intel/lnl_dev/premem_mainboard.c A src/mainboard/intel/lnl_dev/romstage_fsp_params.c A src/mainboard/intel/lnl_dev/smihandler.c A src/mainboard/intel/lnl_dev/spd/Makefile.mk A src/mainboard/intel/lnl_dev/spd/empty.spd.hex A src/mainboard/intel/lnl_dev/spd/lnlrvp_lp5.spd.hex A src/mainboard/intel/lnl_dev/variants/lnlrvp/Makefile.mk A src/mainboard/intel/lnl_dev/variants/lnlrvp/chromeos.fmd A src/mainboard/intel/lnl_dev/variants/lnlrvp/devicetree.cb A src/mainboard/intel/lnl_dev/variants/lnlrvp/early_gpio.c A src/mainboard/intel/lnl_dev/variants/lnlrvp/gpio.c A src/mainboard/intel/lnl_dev/variants/lnlrvp/memory.c 27 files changed, 1,876 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/81875/1
diff --git a/src/mainboard/intel/lnl_dev/Kconfig b/src/mainboard/intel/lnl_dev/Kconfig new file mode 100644 index 0000000..e1c4071 --- /dev/null +++ b/src/mainboard/intel/lnl_dev/Kconfig @@ -0,0 +1,132 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_INTEL_LNL_COMMON + def_bool n + select BOARD_ROMSIZE_KB_32768 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_CHROMEOS + select DRIVERS_I2C_HID + select DRIVERS_I2C_GENERIC + select DRIVERS_GENERIC_MAX98357A + select DRIVERS_INTEL_SOUNDWIRE + select DRIVERS_I2C_MAX98373 + select DRIVERS_USB_ACPI + select DRIVERS_SPI_ACPI + select DRIVERS_SOUNDWIRE_ALC711 + select DRIVERS_SOUNDWIRE_ALC5682 + select DRIVERS_SOUNDWIRE_MAX98373 + select GENERATE_SMBIOS_TABLES + select MAINBOARD_USES_IFD_EC_REGION + select MAINBOARD_USES_IFD_GBE_REGION + select HAVE_SPD_IN_CBFS + select DRIVERS_INTEL_ISH + select DRIVERS_INTEL_MIPI_CAMERA + select FW_CONFIG + select FW_CONFIG_SOURCE_CHROMEEC_CBI if LNL_CHROME_EC + select FW_CONFIG_SOURCE_VPD + select X2APIC_LATE_WORKAROUND + +config BOARD_INTEL_LNLRVP + def_bool n + select BOARD_INTEL_LNL_COMMON + select SOC_INTEL_LUNARLAKE + select CONFIG_DRIVERS_UART_8250IO if ENV_SIMICS + select INTEL_LPSS_UART_FOR_CONSOLE if !ENV_SIMICS + select ENABLE_TCSS_USB_DETECTION + select SOC_INTEL_COMMON_BLOCK_TCSS + select DRIVERS_INTEL_USB4_RETIMER + select DRIVERS_INTEL_PMC + +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + +if BOARD_INTEL_LNL_COMMON + +config CHROMEOS + bool + default y + select GBB_FLAG_FORCE_DEV_SWITCH_ON if BOARD_INTEL_PTLRVP + select GBB_FLAG_FORCE_DEV_BOOT_USB + select GBB_FLAG_FORCE_DEV_BOOT_LEGACY + select GBB_FLAG_FORCE_MANUAL_RECOVERY + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select HAS_RECOVERY_MRC_CACHE + +config DEVICETREE + string + default "variants/lnlrvp/devicetree.cb" if BOARD_INTEL_LNLRVP + +config FMDFILE + depends on VBOOT + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/variants/$(CONFIG_VARIANT_DIR)/chromeos.fmd" + +config MAINBOARD_DIR + string + default "intel/lnl_dev" + +config MAINBOARD_FAMILY + string + default "Intel_lnlrvp" if BOARD_INTEL_LNLRVP + +config MAINBOARD_PART_NUMBER + string + default "lnlrvp" if BOARD_INTEL_LNLRVP + +config VARIANT_DIR + string + default "lnlrvp" if BOARD_INTEL_LNLRVP + +config GBB_HWID + string + depends on CHROMEOS + default "LNLRVP" if BOARD_INTEL_LNLRVP + +config DIMM_SPD_SIZE + int + default 512 + +choice + prompt "ON BOARD EC" + default LNL_CHROME_EC if BOARD_INTEL_LNLRVP + default EC_DETECT + help + This option allows you to select the on board EC to use. + Select whether the board has Intel EC or Chrome EC + +config EC_DETECT + bool "Chrome EC & Window EC" + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_ACPI + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + +config LNL_CHROME_EC + bool "Chrome EC" + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_ESPI + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_ACPI + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select EC_GOOGLE_CHROMEEC_MEC + +config LNL_INTEL_EC + bool "Intel EC" + select EC_ACPI + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC if VBOOT +endchoice + +config VBOOT + select VBOOT_LID_SWITCH + select VBOOT_MOCK_SECDATA + select HAS_RECOVERY_MRC_CACHE + +config UART_FOR_CONSOLE + int + default 0 + +config ENV_SIMICS + def_bool n + +endif diff --git a/src/mainboard/intel/lnl_dev/Kconfig.name b/src/mainboard/intel/lnl_dev/Kconfig.name new file mode 100644 index 0000000..666a5a5 --- /dev/null +++ b/src/mainboard/intel/lnl_dev/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_LNLRVP + bool "Lunarlake RVP" diff --git a/src/mainboard/intel/lnl_dev/Makefile.mk b/src/mainboard/intel/lnl_dev/Makefile.mk new file mode 100644 index 0000000..9935bb6 --- /dev/null +++ b/src/mainboard/intel/lnl_dev/Makefile.mk @@ -0,0 +1,27 @@ +## SPDX-License-Identifier: GPL-2.0-only + +subdirs-y += spd + +bootblock-y += bootblock.c +bootblock-$(CONFIG_CHROMEOS) += chromeos.c +bootblock-y += board_id.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += romstage_fsp_params.c +romstage-y += board_id.c + +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += mainboard.c +ramstage-y += board_id.c + +smm-y += smihandler.c +ramstage-y += ec.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c + +subdirs-y += variants/$(VARIANT_DIR) +subdirs-y += ../common +subdirs-y += variants + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/intel/lnl_dev/board_id.c b/src/mainboard/intel/lnl_dev/board_id.c new file mode 100644 index 0000000..9587c34 --- /dev/null +++ b/src/mainboard/intel/lnl_dev/board_id.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boardid.h> +#include <console/console.h> +#include <ec/acpi/ec.h> +#include <ec/google/chromeec/ec.h> +#include <stdint.h> +#include <types.h> +#include <baseboard/board_id.h> +#include <baseboard/variants.h> + +static uint32_t get_board_id_via_ext_ec(void) +{ + uint32_t id = BOARD_ID_UNKNOWN; + +#if CONFIG(EC_GOOGLE_CHROMEEC) + if (google_chromeec_get_board_version(&id)) + id = BOARD_ID_UNKNOWN; +#endif + + return id; +} + +/* Get Board ID via EC I/O port write/read */ +int get_board_id(void) +{ + static int id = BOARD_ID_UNKNOWN; + + if (id == BOARD_ID_UNKNOWN) { + id = get_board_id_via_ext_ec(); + printk(BIOS_INFO, "id from Chrome EC 0x%x\n", (unsigned int)id); + if (id == BOARD_ID_UNKNOWN) { + if (send_ec_command(EC_FAB_ID_CMD) == 0) { + id = recv_ec_data() << 8; + id |= recv_ec_data(); + printk(BIOS_INFO, "id from Windows EC 0x%x\n", + (unsigned int)id); + } + } + } + return (id & BOARD_ID_MASK); +} diff --git a/src/mainboard/intel/lnl_dev/board_info.txt b/src/mainboard/intel/lnl_dev/board_info.txt new file mode 100644 index 0000000..f545af5 --- /dev/null +++ b/src/mainboard/intel/lnl_dev/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Lunarlake rvp +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/lnl_dev/bootblock.c b/src/mainboard/intel/lnl_dev/bootblock.c new file mode 100644 index 0000000..38199a1 --- /dev/null +++ b/src/mainboard/intel/lnl_dev/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootblock_common.h> +#include <baseboard/variants.h> + +void bootblock_mainboard_early_init(void) +{ + variant_configure_early_gpio_pads(); +} diff --git a/src/mainboard/intel/lnl_dev/chromeos.c b/src/mainboard/intel/lnl_dev/chromeos.c new file mode 100644 index 0000000..07b76a3 --- /dev/null +++ b/src/mainboard/intel/lnl_dev/chromeos.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <bootmode.h> +#include <boot/coreboot_tables.h> +#include <types.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <baseboard/gpio.h> +#include <baseboard/gpio.h> +#include <baseboard/variants.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {-1, ACTIVE_HIGH, 0, "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +#if !CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) +int get_lid_switch(void) +{ + /* Lid always open */ + return 1; +} + +int get_recovery_mode_switch(void) +{ + return 0; +} +#endif /*!CONFIG(EC_GOOGLE_CHROMEEC_SWITCHES) */ + +int get_write_protect_state(void) +{ + /* No write protect */ + return 0; +} +#if 0 +void mainboard_chromeos_acpi_generate(void) +{ + chromeos_acpi_gpio_generate(); +} +#endif diff --git a/src/mainboard/intel/lnl_dev/dsdt.asl b/src/mainboard/intel/lnl_dev/dsdt.asl new file mode 100644 index 0000000..a64007b --- /dev/null +++ b/src/mainboard/intel/lnl_dev/dsdt.asl @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +#include <baseboard/ec.h> +#include <baseboard/gpio.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include <cpu/intel/common/acpi/cpu.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + + Scope (_SB) { + Device (PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/lnl_dev/acpi/southbridge.asl> + #include <soc/intel/lnl_dev/acpi/tcss.asl> + } + } + + +#if CONFIG(EC_GOOGLE_CHROMEEC) + /* Chrome OS Embedded Controller */ + Scope (_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include <ec/google/chromeec/acpi/superio.asl> + /* ACPI code for EC functions */ + #include <ec/google/chromeec/acpi/ec.asl> + } +#endif + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/intel/lnl_dev/ec.c b/src/mainboard/intel/lnl_dev/ec.c new file mode 100644 index 0000000..0c362ce --- /dev/null +++ b/src/mainboard/intel/lnl_dev/ec.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +#include <ec/ec.h> +#include <ec/google/chromeec/ec.h> +#include <baseboard/ec.h> + +void mainboard_ec_init(void) +{ + const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, + }; + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} diff --git a/src/mainboard/intel/lnl_dev/fw_config.c b/src/mainboard/intel/lnl_dev/fw_config.c new file mode 100644 index 0000000..78e76f7 --- /dev/null +++ b/src/mainboard/intel/lnl_dev/fw_config.c @@ -0,0 +1,88 @@ +#include <bootstate.h> +#include <console/console.h> +#include <fw_config.h> +#include <inttypes.h> +#include <baseboard/gpio.h> + +static const struct pad_config i2s_enable_pads[] = { + /* Audio: I2S0 + GPP_D9: I2S_MCLK1_OUT + GPP_D10: I2S0_SCLK_HDR + GPP_D11: I2S0_SFRM_HDR + GPP_D12: I2S0_TXD_HDR + GPP_D13: I2S0_RXD_HDR + */ + PAD_CFG_NF(GPP_D9, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF2), + + /* Audio: I2S1 + GPP_S0: I2S1_SCLK_HDR + GPP_S1: I2S1_SFRM_HDR + GPP_S2: I2S1_TXD_HDR + GPP_S3: I2S1_RXD_HDR + */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF6), + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF6), + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF6), + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF6), + + /* Audio: DMIC + GPP_S6: DMIC_CLK_A1 + GPP_S7: DMIC_DATA1 + */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF3), + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF3), + +}; + +static const struct pad_config sndw_enable_pads[] = { + /* Soundwire - External codec - JE Header */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), + /* DMIC - JD Header */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF3), + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF3), + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF3), + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF3), +}; + +static const struct pad_config audio_disable_pads[] = { + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), +}; + +static void fw_config_handle(void *unused) +{ + if (fw_config_probe(FW_CONFIG(AUDIO, NONE))) { + printk(BIOS_INFO, "Configure GPIOs for no audio.\n"); + gpio_configure_pads(audio_disable_pads, ARRAY_SIZE(audio_disable_pads)); + } + printk(BIOS_INFO, "FW config 0x%" PRIx64 "\n", fw_config_get()); + if (fw_config_probe(FW_CONFIG(AUDIO, LNL_ALC1019_ALC5682I_I2S)) || + fw_config_probe(FW_CONFIG(AUDIO, LNL_ALC5682I_MAX9857A_I2S))) { + printk(BIOS_INFO, "Configure GPIOs for I2S audio.\n"); + gpio_configure_pads(i2s_enable_pads, ARRAY_SIZE(i2s_enable_pads)); + } + printk(BIOS_INFO, "FW config 0x%" PRIx64 "\n", fw_config_get()); + if (fw_config_probe(FW_CONFIG(AUDIO, LNL_MAX98373_ALC5682_SNDW))) { + printk(BIOS_INFO, "Configure GPIOs for SoundWire audio (ext codec).\n"); + gpio_configure_pads(sndw_enable_pads, ARRAY_SIZE(sndw_enable_pads)); + } +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/intel/lnl_dev/include/baseboard/board_id.h b/src/mainboard/intel/lnl_dev/include/baseboard/board_id.h new file mode 100644 index 0000000..2988127 --- /dev/null +++ b/src/mainboard/intel/lnl_dev/include/baseboard/board_id.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MAINBOARD_COMMON_BOARD_ID_H_ +#define _MAINBOARD_COMMON_BOARD_ID_H_ + +/* Board/FAB ID Command */ +#define EC_FAB_ID_CMD 0x0d +/* Bit 5:0 for Board ID */ +#define BOARD_ID_MASK 0x3f + +/* + * Returns board information (board id[15:8] and + * Fab info[7:0]) on success and < 0 on error + */ +int get_board_id(void); + +#endif /* _MAINBOARD_COMMON_BOARD_ID_H_ */ diff --git a/src/mainboard/intel/lnl_dev/include/baseboard/ec.h b/src/mainboard/intel/lnl_dev/include/baseboard/ec.h new file mode 100644 index 0000000..c018299 --- /dev/null +++ b/src/mainboard/intel/lnl_dev/include/baseboard/ec.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include <ec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <baseboard/gpio.h> + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3 with lid or power button or key press or + * mode change event. + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/intel/lnl_dev/include/baseboard/gpio.h b/src/mainboard/intel/lnl_dev/include/baseboard/gpio.h new file mode 100644 index 0000000..de0adf6 --- /dev/null +++ b/src/mainboard/intel/lnl_dev/include/baseboard/gpio.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/lnl_dev/include/baseboard/variants.h b/src/mainboard/intel/lnl_dev/include/baseboard/variants.h new file mode 100644 index 0000000..2337caa --- /dev/null +++ b/src/mainboard/intel/lnl_dev/include/baseboard/variants.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include <soc/gpio.h> +#include <soc/meminit.h> +#include <stdint.h> +#include <vendorcode/google/chromeos/chromeos.h> + +enum lnl_boardid { + LNLM_LP5_RVP = 0x01, + PTLP_LP5_RVP = 0x31, +}; + +/* The next set of functions return the gpio table and fill in the number of + * entries for each table. */ +const struct cros_gpio *variant_cros_gpios(size_t *num); +/* Functions to configure GPIO as per variant schematics */ +void variant_configure_gpio_pads(void); +void variant_configure_early_gpio_pads(void); + +size_t variant_memory_sku(void); +const struct mb_cfg *variant_memory_params(void); +#endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/lnl_dev/mainboard.c b/src/mainboard/intel/lnl_dev/mainboard.c new file mode 100755 index 0000000..b0e4ec2 --- /dev/null +++ b/src/mainboard/intel/lnl_dev/mainboard.c @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/device.h> +#include <drivers/intel/gma/opregion.h> +#include <drivers/intel/mipi_camera/chip.h> +#include <ec/ec.h> +#include <soc/gpio.h> +#include <soc/pci_devs.h> +#include <soc/ramstage.h> +#include <soc/usb.h> +#include <soc/soc_info.h> +#include <smbios.h> +#include <stdint.h> +#include <string.h> +#include <console/console.h> +#include <baseboard/board_id.h> +#include <baseboard/gpio.h> +#include <baseboard/variants.h> + +const char *smbios_system_sku(void) +{ + static char sku_str[7] = ""; + uint8_t sku_id = get_board_id(); + + snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); + return sku_str; +} + +const char *mainboard_vbt_filename(void) +{ + return "vbt.bin"; +} + +static void mainboard_devtree_update(void) +{ +} + +void mainboard_update_soc_chip_config(struct soc_intel_lnl_dev_config *cfg) +{ +} + +static void mainboard_init(void *chip_info) +{ + variant_configure_gpio_pads(); + + if (CONFIG(EC_GOOGLE_CHROMEEC)) + mainboard_ec_init(); + + mainboard_devtree_update(); +} + +static void mainboard_enable(struct device *dev) +{ + /* TODO: Enable mainboard */ +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/intel/lnl_dev/premem_mainboard.c b/src/mainboard/intel/lnl_dev/premem_mainboard.c new file mode 100644 index 0000000..8cc8533 --- /dev/null +++ b/src/mainboard/intel/lnl_dev/premem_mainboard.c @@ -0,0 +1,54 @@ +#include <soc/romstage.h> +#include <console/console.h> +#include <fw_config.h> +#include <inttypes.h> +#include <baseboard/board_id.h> +#include <baseboard/variants.h> + +static void rp_cfg(struct soc_intel_lnl_dev_config *cfg, uint8_t rp, uint8_t clk, + uint8_t clk_req, uint8_t flags) +{ + cfg->pcie_rp[rp].clk_src = clk; + cfg->pcie_rp[rp].clk_req = clk_req; + cfg->pcie_rp[rp].flags = flags; +} + +static void update_rp_configuration(struct soc_intel_lnl_dev_config *cfg, + uint8_t board_id) +{ + uint8_t flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR; + + switch (board_id) { + case LNLM_LP5_RVP: + rp_cfg(cfg, 0, 0, 0, flags); + rp_cfg(cfg, 4, 1, 1, flags); + rp_cfg(cfg, 5, 4, 4, flags); + rp_cfg(cfg, 6, 2, 2, flags); + rp_cfg(cfg, 7, 3, 3, flags); + rp_cfg(cfg, 8, 5, 5, flags); + printk(BIOS_INFO, "LNLM_RVP RP configuration\n"); + break; + default: + break; + } +} + +static void update_debug_configuration(struct soc_intel_lnl_dev_config *cfg, + uint8_t board_id) +{ + printk(BIOS_INFO, "FW config 0x%" PRIx64 "\n", fw_config_get()); + + if (fw_config_probe(FW_CONFIG(DEBUG, RMT))) { + cfg->RMT = 1; + printk(BIOS_INFO, "RMT enabled\n"); + } +} + +void mainboard_update_premem_soc_chip_config(struct soc_intel_lnl_dev_config *cfg) +{ + uint8_t board_id = get_board_id(); + + printk(BIOS_INFO, "%s: board_id: 0x%x\n", __func__, board_id); + update_rp_configuration(cfg, board_id); + update_debug_configuration(cfg, board_id); +} diff --git a/src/mainboard/intel/lnl_dev/romstage_fsp_params.c b/src/mainboard/intel/lnl_dev/romstage_fsp_params.c new file mode 100644 index 0000000..aefa8c6 --- /dev/null +++ b/src/mainboard/intel/lnl_dev/romstage_fsp_params.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <console/console.h> +#include <fsp/api.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <string.h> +#include <soc/meminit.h> +#include <baseboard/board_id.h> +#include <baseboard/variants.h> + +#define SPD_ID_MASK 0x1 + +static size_t get_spd_index(void) +{ + uint8_t board_id = get_board_id(); + size_t spd_index; + + printk(BIOS_INFO, "board id is 0x%x\n", board_id); + + spd_index = board_id & SPD_ID_MASK; + + printk(BIOS_INFO, "SPD index is 0x%x\n", (unsigned int)spd_index); + return spd_index; +} + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + const struct mb_cfg *mem_config = variant_memory_params(); + const bool half_populated = false; + + const struct mem_spd lp4_lp5_spd_info = { + .topo = MEM_TOPO_MEMORY_DOWN, + .cbfs_index = get_spd_index(), + }; + + int board_id = get_board_id(); + + switch (board_id) { + case LNLM_LP5_RVP: + memcfg_init(memupd, mem_config, &lp4_lp5_spd_info, half_populated); + break; + case PTLP_LP5_RVP: + memcfg_init(memupd, mem_config, &lp4_lp5_spd_info, half_populated); + break; + default: + die("Unknown board id = 0x%x\n", board_id); + } +} diff --git a/src/mainboard/intel/lnl_dev/smihandler.c b/src/mainboard/intel/lnl_dev/smihandler.c new file mode 100644 index 0000000..a3b4323 --- /dev/null +++ b/src/mainboard/intel/lnl_dev/smihandler.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/smm.h> +#include <intelblocks/smihandler.h> +#include <baseboard/ec.h> + +void mainboard_smi_espi_handler(void) +{ + if (!CONFIG(EC_GOOGLE_CHROMEEC)) + return; + + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (!CONFIG(EC_GOOGLE_CHROMEEC)) + return; + + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + if (CONFIG(EC_GOOGLE_CHROMEEC)) + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS); + + return 0; +} diff --git a/src/mainboard/intel/lnl_dev/spd/Makefile.mk b/src/mainboard/intel/lnl_dev/spd/Makefile.mk new file mode 100644 index 0000000..7ee6531 --- /dev/null +++ b/src/mainboard/intel/lnl_dev/spd/Makefile.mk @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +SPD_SOURCES = empty # 0b000 +SPD_SOURCES += lnlrvp_lp5 # 0b001 diff --git a/src/mainboard/intel/lnl_dev/spd/empty.spd.hex b/src/mainboard/intel/lnl_dev/spd/empty.spd.hex new file mode 100644 index 0000000..67b46cd --- /dev/null +++ b/src/mainboard/intel/lnl_dev/spd/empty.spd.hex @@ -0,0 +1,32 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/lnl_dev/spd/lnlrvp_lp5.spd.hex b/src/mainboard/intel/lnl_dev/spd/lnlrvp_lp5.spd.hex new file mode 100644 index 0000000..594e7e7 --- /dev/null +++ b/src/mainboard/intel/lnl_dev/spd/lnlrvp_lp5.spd.hex @@ -0,0 +1,32 @@ +23 01 15 0E 86 21 B9 08 00 40 00 00 02 01 00 00 +48 00 07 FF 92 55 05 00 AA 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F 3E 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 2C 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 2C +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/lnl_dev/variants/lnlrvp/Makefile.mk b/src/mainboard/intel/lnl_dev/variants/lnlrvp/Makefile.mk new file mode 100644 index 0000000..b554782 --- /dev/null +++ b/src/mainboard/intel/lnl_dev/variants/lnlrvp/Makefile.mk @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019-2020 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += early_gpio.c +ramstage-y += gpio.c +romstage-y += memory.c diff --git a/src/mainboard/intel/lnl_dev/variants/lnlrvp/chromeos.fmd b/src/mainboard/intel/lnl_dev/variants/lnlrvp/chromeos.fmd new file mode 100644 index 0000000..e6b2820 --- /dev/null +++ b/src/mainboard/intel/lnl_dev/variants/lnlrvp/chromeos.fmd @@ -0,0 +1,43 @@ +FLASH 32M { + SI_ALL 12M { + SI_DESC 16K + SI_EC 512K + SI_ME + } + SI_BIOS 20M { + RW_SECTION_A 7M { + VBLOCK_A 64K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + } + RW_SECTION_B 7M { + VBLOCK_B 64K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + } + RW_MISC 1M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } + # RW_LEGACY needs to be minimum of 1MB + RW_LEGACY(CBFS) 1M + WP_RO 4M { + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 16K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/intel/lnl_dev/variants/lnlrvp/devicetree.cb b/src/mainboard/intel/lnl_dev/variants/lnlrvp/devicetree.cb new file mode 100644 index 0000000..00e51d7 --- /dev/null +++ b/src/mainboard/intel/lnl_dev/variants/lnlrvp/devicetree.cb @@ -0,0 +1,490 @@ +fw_config + field DEBUG 0 1 + option NONE 0 + option RMT 1 + end + field AUDIO 8 10 + option NONE 0 + option LNL_ALC1019_ALC5682I_I2S 1 + option LNL_MAX98373_ALC5682_SNDW 2 + option LNL_ALC711_SNDW 3 + option LNL_ALC5682I_MAX9857A_I2S 4 + end +end + +chip soc/intel/lnl_dev + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + + # Enable HECI1 interface + register "HeciEnabled" = "1" + + # FSP configuration + + # Enable CNVi BT + register "cnvi_bt_core" = "true" + + # Enable CNVi WiFi + register "cnvi_wifi_core" = "true" + + #USB2.0 configuration + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # Type-A con1 + register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # Type-A con2 + register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port2 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN + + #USB3.2 configuration + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A con1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-A con2 + + #Type-C configuration + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + # This disabled autonomous GPIO power management for early PO + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" + + # Enable EDP in PortA + register "ddi_port_A_config" = "1" + # Enable EDP in PortB + register "ddi_port_B_config" = "1" + # Enable HDMI in Port B + register "ddi_ports_config" = "{ + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + + # Enable IBECC (In Band Error Correction Code) + register "ibecc.enable" = "false" + register "ibecc.mode" = "CONFIG(LUNARLAKE_ENABLE_IBECC) ? IBECC_MODE_PER_REGION : IBECC_MODE_NONE" + + # TCSS USB3 + register "tcss_aux_ori" = "0" + + register "s0ix_enable" = "true" + register "dptf_enable" = "0" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoI3cMode" = "{ + [PchSerialIoIndexI3C0] = PchSerialIoPci, + [PchSerialIoIndexI3C1] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoPci, + }" + + # HD Audio + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "10" + + register "cnvi_bt_audio_offload" = "true" + + # Intel Common SoC Config + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device ref igpu on end + device ref ipu on + chip drivers/intel/mipi_camera + register "acpi_uid" = "0x50000" + register "acpi_name" = ""IPU0"" + register "device_type" = "INTEL_ACPI_CAMERA_CIO2" + register "cio2_num_ports" = "2" + register "cio2_lanes_used" = "{2,2}" + register "cio2_lane_endpoint[0]" = ""^I2C1.CAM0"" + register "cio2_lane_endpoint[1]" = ""^I2C0.CAM1"" + register "cio2_prt[0]" = "2" + register "cio2_prt[1]" = "1" + device generic 0 on end + end + end + device ref dtt off end + device ref npu on end + device ref heci1 on end + device ref thc0 off end + device ref thc1 off end + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tbt_pcie_rp2 on end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + use tcss_usb3_port0 as dfp[0].typec_port + device generic 0 on end + end + chip drivers/intel/usb4/retimer + register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + use tcss_usb3_port1 as dfp[1].typec_port + device generic 0 on end + end + end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + use tcss_usb3_port2 as dfp[0].typec_port + device generic 0 on end + end + end + + device ref pcie_rp1 on + # Enable PCH PCIE RP 1 using CLK 4 + register "pcie_rp[PCIE_RP(1)]" = "{ + .clk_src = 4, + .clk_req = 4, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + end # GbE LAN + device ref pcie_rp2 on + # Enable PCH PCIE RP 2 using CLK 0 + register "pcie_rp[PCIE_RP(2)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + end #x1 PCIe DT Slot + device ref pcie_rp3 on + # Enable PCH PCIE RP 3 using CLK 1 + register "pcie_rp[PCIE_RP(3)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + end # WLAN M.2 + device ref pcie_rp4 on + # Enable PCH PCIE RP 4 using CLK 2 + register "pcie_rp[PCIE_RP(4)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + end # WWAN M.2 + device ref pcie_rp5 on + # Enable PCH PCIE RP 5 using CLK 3 + register "pcie_rp[PCIE_RP(5)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + end # Gen5 M.2 SSD + device ref pcie_rp6 on + # Enable PCH PCIE RP 6 using CLK 5 + register "pcie_rp[PCIE_RP(6)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + end # Gen5 M.2 SSD 2 + device ref ish off + chip drivers/intel/ish + register "firmware_name" = ""lnlrvp_ish.bin"" + device generic 0 on end + end + end + + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 3))" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WLAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 2))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 3))" + device ref usb3_port2 on end + end + end + end + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + + device ref i2c0 on end + device ref i2c1 on end + device ref i2c2 on end + device ref i2c3 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_S4_IRQ)" + register "probed" = "1" + # jd_src RT5668_JD1 = 1, RT5682_JD_NULL = 0 + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + probe AUDIO LNL_ALC5682I_MAX9857A_I2S + probe AUDIO LNL_ALC1019_ALC5682I_I2S + end + end + # Ref config #5 for Chrome, transducer card config 5A + #+-------------------+-------------------+ + #| Speaker Amp | Assignment | + #+-------------------+-------------------+ + #| SPK 0 | left | + #| SPK 1 | right | + #| SPK 2 | top left | + #| SPK 3 | top right | + #+-------------------+-------------------+ + chip drivers/i2c/generic + register "hid" = ""10EC1019"" + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "0" + device i2c 28 on + probe AUDIO LNL_ALC1019_ALC5682I_I2S + end + end + chip drivers/i2c/generic + register "hid" = ""10EC1019"" + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "1" + device i2c 29 on + probe AUDIO LNL_ALC1019_ALC5682I_I2S + end + end + chip drivers/i2c/generic + register "hid" = ""10EC1019"" + register "desc" = ""Realtek SPK AMP TL"" + register "uid" = "2" + device i2c 2a on + probe AUDIO LNL_ALC1019_ALC5682I_I2S + end + end + chip drivers/i2c/generic + register "hid" = ""10EC1019"" + register "desc" = ""Realtek SPK AMP TR"" + register "uid" = "3" + device i2c 2b on + probe AUDIO LNL_ALC1019_ALC5682I_I2S + end + end + end # I2C3 + device ref i2c4 on end + device ref i2c5 on end + device ref i3c on end + + device ref ufs off end + device ref uart0 on end + device ref uart1 off end + device ref uart2 off end + + device ref gspi0 on end + device ref gspi1 on end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port0 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 1 alias conn1 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port5 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 2 alias conn2 on end + end + end + end + end + device ref smbus on end + device ref hda on + chip drivers/intel/soundwire + device generic 0 on + chip drivers/soundwire/alc711 + # SoundWire Link 0 ID 1 + register "desc" = ""Headset Codec"" + device generic 0.1 on + probe AUDIO LNL_ALC711_SNDW + end + end + chip drivers/soundwire/alc5682 + # SoundWire Link 0 ID 1 + register "desc" = ""Headset Codec"" + device generic 0.1 on + probe AUDIO LNL_MAX98373_ALC5682_SNDW + end + end + chip drivers/soundwire/max98373 + # SoundWire Link 2 ID 3 + register "desc" = ""Left Speaker Amp"" + device generic 2.3 on + probe AUDIO LNL_MAX98373_ALC5682_SNDW + end + end + chip drivers/soundwire/max98373 + # SoundWire Link 0 ID 7 + register "desc" = ""Right Speaker Amp"" + device generic 0.7 on + probe AUDIO LNL_MAX98373_ALC5682_SNDW + end + end + end + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_S5)" + register "sdmode_delay" = "5" + device generic 0 on + probe AUDIO LNL_ALC5682I_MAX9857A_I2S + end + end + end + end + device ref soc_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + use conn2 as mux_conn[2] + device pnp 0c09.0 on end + end + end + end +end diff --git a/src/mainboard/intel/lnl_dev/variants/lnlrvp/early_gpio.c b/src/mainboard/intel/lnl_dev/variants/lnlrvp/early_gpio.c new file mode 100644 index 0000000..afa8a56 --- /dev/null +++ b/src/mainboard/intel/lnl_dev/variants/lnlrvp/early_gpio.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <commonlib/helpers.h> +#include <soc/soc_info.h> +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <baseboard/board_id.h> + + +/* Early pad configuration in bootblock */ +static const struct pad_config lnlmrvp_early_gpio_table[] = { + /* UART0*/ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /*GPP_H8 : UART0_RXD */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /*GPP_H9 : UART0_TXD*/ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), /*GPP_H10 : UART0_RTS_B*/ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), /*GPP_H11 : UART0_CTS_B*/\ + PAD_CFG_GPO(GPP_S5, 1, DEEP), /*GPP_S5 : SPK_EN*/ + PAD_CFG_GPI_INT(GPP_S4, NONE, PLTRST, EDGE_BOTH), /*GPP_S4 : HS_IRQ*/ +}; + +static const struct pad_config early_wwan_on_gpio_table[] = { + /* M.2 WWAN */ + PAD_CFG_GPO(GPP_A9, 1, DEEP), /* M.2_WWAN_FCP_OFF_N */ + PAD_CFG_GPO(GPP_B20, 1, DEEP), /* WWAN_PWREN */ + PAD_CFG_GPO(GPP_D3, 1, DEEP), /* M.2_WWAN_PERST_GPIO_N */ + PAD_CFG_GPI_SCI(GPP_E2, NONE, DEEP, EDGE_BOTH, INVERT), /* M.2_WWAN_WAKE_GPIO_N */ + PAD_CFG_GPO(GPP_E8, 0, DEEP), /* M.2_WWAN_RST_N */ +}; + + +void variant_configure_early_gpio_pads(void) +{ + uint8_t board_id = get_board_id(); + + switch (board_id) { + case LNLM_LP5_RVP: + printk(BIOS_DEBUG, "configuring LNLM RVP early gpios\n"); + gpio_configure_pads(lnlmrvp_early_gpio_table, + ARRAY_SIZE(lnlmrvp_early_gpio_table)); + break; + default: + printk(BIOS_DEBUG, "bypass early gpios configuration\n"); + } + + gpio_configure_pads(early_wwan_on_gpio_table, ARRAY_SIZE(early_wwan_on_gpio_table)); +} + diff --git a/src/mainboard/intel/lnl_dev/variants/lnlrvp/gpio.c b/src/mainboard/intel/lnl_dev/variants/lnlrvp/gpio.c new file mode 100644 index 0000000..47ac709 --- /dev/null +++ b/src/mainboard/intel/lnl_dev/variants/lnlrvp/gpio.c @@ -0,0 +1,394 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <commonlib/helpers.h> +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <baseboard/board_id.h> + +/* Pad configuration in ramstage*/ +static const struct pad_config lnlmrvp_gpio_table[] = { + /* GPP_A */ + /* GPP_A00 : GPP_A00 ==> ESPI_SOC_IO0_R configured on reset, do not touch */ + /* GPP_A01 : GPP_A01 ==> ESPI_SOC_IO1_R configured on reset, do not touch */ + /* GPP_A02 : GPP_A02 ==> ESPI_SOC_IO2_R configured on reset, do not touch */ + /* GPP_A03 : GPP_A03 ==> ESPI_SOC_IO3_R configured on reset, do not touch */ + /* GPP_A04 : GPP_A04 ==> ESPI_SOC_CS0_L configured on reset, do not touch */ + /* GPP_A05 : GPP_A05 ==> ESPI_SOC_CLK_R configured on reset, do not touch */ + /* GPP_A06 : GPP_A06 ==> ESPI_SOC_RESET_L configured on reset, do not touch */ + + /* GPP_A8: X1_PCIE_SLOT1_PWR_EN */ + PAD_CFG_GPO(GPP_A8, 1, PLTRST), + /* GPP_A11: M2_SSD_RST_N */ + PAD_CFG_GPO(GPP_A11, 1, PLTRST), + /* GPP_A12: X1_DT_PCIE_RST_N */ + PAD_CFG_GPO(GPP_A12, 1, PLTRST), + /* GPP_A15: DNX_FORCE_RELOAD */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + + /* GPP_B */ + /* GPP_B0: DG_TBT_I2C_SCL_PDAIC1 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* GPP_B1: DG_TBT_I2C_SDA_PDAIC1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* GPP_B2: ISH_I2C0_SDA_SNSR_HDR */ + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF3), + /* GPP_B3: ISH_I2C0_SCL_SNSR_HDR */ + PAD_CFG_NF(GPP_B3, NONE, DEEP, NF3), + /* GPP_B4: ISH_GP_0_SNSR_HDR_R */ + PAD_CFG_NF(GPP_B4, NONE, DEEP, NF4), + /* GPP_B5: ISH_GP_1_SNSR_HDR_R */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF4), + /* GPP_B6: ISH_GP_2_SNSR_HDR_R */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF4), + /* GPP_B7: ISH_GP_3_SNSR_HDR */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF4), + /* GPP_B8: ISH_GP_4_SNSR_HDR_R */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF4), + /* GPP_B9: WIFI_WAKE_N */ + PAD_CFG_GPI_SCI(GPP_B9, NONE, DEEP, LEVEL, INVERT), + /* GPP_B10: CRD3_PWREN */ + PAD_CFG_GPO(GPP_B10, 1, PLTRST), + /* GPP_B11: COINLESS_MODE_SELECT */ + PAD_CFG_GPI(GPP_B11, NONE, PLTRST), + /* GPP_B12: PM_SLP_S0_N */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* GPP_B13: PLT_RST_N */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* GPP_B14: CRD_CAM_STROBE */ + PAD_CFG_GPO(GPP_B14, 1, PLTRST), + /* GPP_B15: NC */ + PAD_NC(GPP_B15, NONE), + /* GPP_B16: NC */ + PAD_NC(GPP_B16, NONE), + /* GPP_B17: NC */ + PAD_NC(GPP_B17, NONE), + /* GPP_B18: ISH_I2C2_SDA_SNSR_HDR */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* GPP_B19: ISH_I2C2_SCL_SNSR_HDR */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* GPP_B20: WWAN_PWREN */ + /* PAD_CFG_GPO(GPP_B20, 1, DEEP), */ + /* GPP_B21: TCP_RETIMER_FORCE_PWR */ + PAD_CFG_GPO(GPP_B21, 0, PLTRST), + /* GPP_B22: ISH_GP_5_SNSR_HDR */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4), + /* GPP_B23: ISH_GP_6_SNSR_HDR_R */ + PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4), + + /* GPP_C */ + /* GPP_C0: NC */ + PAD_NC(GPP_C0, NONE), + /* GPP_C1: NC */ + PAD_NC(GPP_C1, NONE), + /* GPP_C2: SPI_TPM_INT_N */ + PAD_CFG_GPI_SCI(GPP_C2, NONE, PLTRST, EDGE_BOTH, INVERT), + /* GPP_C3: SML0_CLK_R */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* GPP_C4: SML0_DATA_R */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + /* GPP_C5: CRD3_PRIVACY_LED */ + PAD_CFG_GPO(GPP_C5, 1, PLTRST), + /* GPP_C6: SML1_CLK_R */ + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), + /* GPP_C7: SML1_DATA_R */ + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), + /* GPP_C8: CRD2_PWREN */ + PAD_CFG_GPO(GPP_C8, 1, PLTRST), + /* GPP_C9: CLKREQ0_GEN4_X1_DT_SLOT1_N */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* GPP_C10: M.2_WLAN_CLKREQ1_N */ + PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), + /* GPP_C11: SRCCLKREQ2_WWAN_N */ + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), + /* GPP_C12: CLKREQ3_M2_SSD_GEN5_LS_N */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + /* GPP_C13: CLKREQ3_M2_SSD_GEN5_LS_N */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + /* GPP_C14: NC */ + PAD_NC(GPP_C14, NONE), + /* GPP_C15: CRD_CLK_EN */ + PAD_CFG_GPO(GPP_C15, 0, PLTRST), + /* GPP_C16: TBT_LSX0_TXD */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* GPP_C17: TBT_LSX0_RXD */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* GPP_C18: TBT_LSX1_TXD */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* GPP_C19: TBT_LSX1_RXD */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* GPP_C20: TBT_LSX2_TXD */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* GPP_C21: TBT_LSX2_RXD */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + + /* GPP_D */ + /* GPP_D0: CRD2_IMGCLKOUT_1 */ + PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), + /* GPP_D1: BT_RF_KILL_N */ + PAD_CFG_GPO(GPP_D1, 1, PLTRST), + /* GPP_D2: WIFI_RF_KILL_N */ + PAD_CFG_GPO(GPP_D2, 1, PLTRST), + /* GPP_D3: M.2_WWAN_PERST_GPIO_N */ + /*PAD_CFG_GPO(GPP_D3, 1, DEEP),*/ + /* GPP_D4: CRD1_IMGCLKOUT_0 */ + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), + /* GPP_D5: ISH_SPI_CS_N_SNSR_HDR */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), + /* GPP_D6: ISH_SPI_CLK_SNSR_HDR */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), + /* GPP_D7: ISH_SPI_MISO_SNSR_HDR */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF3), + /* GPP_D8: ISH_SPI_MOSI_SNSR_HDR */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF3), + /* GPP_D9: I2S_MCLK1_OUT */ + PAD_CFG_NF(GPP_D9, NONE, DEEP, NF2), + /* GPP_D10: HDA_BCLK_I2S0_SCLK_HDR */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), + /* GPP_D11: HDA_SYNC_I2S0_SFRM_HDR */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), + /* GPP_D12: HDA_SDO_I2S0_TXD_HDR */ + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2), + /* GPP_D13: HDA_SDI0_I2S0_RXD_HDR */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF2), + /* GPP_D14: NC */ + PAD_NC(GPP_D14, NONE), + /* GPP_D15: NC */ + PAD_NC(GPP_D15, NONE), + /* GPP_D16: HDA_SDI1_HDR */ + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), + /* GPP_D17: HDA_RST_N_HDR */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + /* GPP_D18: NC */ + PAD_NC(GPP_D18, NONE), + /* GPP_D19: NC */ + PAD_NC(GPP_D19, NONE), + /* GPP_D20: NC */ + PAD_NC(GPP_D20, NONE), + /* GPP_D21: GPP_D21_UFS_REFCLK */ + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), + /* GPP_D22: USBC_TCPC_SBU1_P0 */ + PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), + /* GPP_D23: USBC_TCPC_SBU2_P0 */ + PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), + + /* GPP_E */ + /* GPP_E0: NC */ + PAD_NC(GPP_E0, NONE), + /* GPP_E1: NC */ + PAD_NC(GPP_E1, NONE), + /* GPP_E2: M.2_WWAN_WAKE_GPIO_N */ + /* PAD_CFG_GPI_SCI(GPP_E2, NONE, DEEP, EDGE_BOTH, INVERT), */ + /* GPP_E3: M2_PCH_SSD_PWREN */ + PAD_CFG_GPO(GPP_E3, 1, PLTRST), + /* GPP_E4: DDIA_EDP_HPD */ + PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), + /* GPP_E5: ISH_GP_7_SNSR_HDR */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF4), + /* GPP_E6: CAM_SECURE */ + PAD_CFG_GPI(GPP_E6, NONE, PLTRST), + /* GPP_E7: TCH_PNL1_PWR_EN */ + PAD_CFG_GPO(GPP_E7, 1, PLTRST), + /* GPP_E8: M.2_WWAN_RST_N */ + /* PAD_CFG_GPO(GPP_E8, 1, PLTRST),*/ + /* GPP_E9: DDIA_EDP_HPD */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* GPP_E10: TCH_PNL1_PWR_EN */ + PAD_CFG_GPO(GPP_E10, 1, PLTRST), + /* GPP_E11: THC0_SPI1_CLK_TCH_PNL1_VISA2CH1_CLK */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3), + /* GPP_E12: THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1_VISA2CH1_D0 */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3), + /* GPP_E13: THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1_VISA2CH1_D1 */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3), + /* GPP_E14: THC0_SPI1_IO_2_TCH_PNL1_VISA2CH1_D2 */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3), + /* GPP_E15: THC0_SPI1_IO_3_TCH_PNL1_VISA2CH1_D3 */ + PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3), + /* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1_VISA2CH1_D4 */ + PAD_CFG_NF(GPP_E16, NONE, DEEP, NF3), + /* GPP_E17: THC0_SPI1_CS0_N_TCH_PNL1_VISA2CH1_D5 */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF3), + /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1_VISA2CH1_D6 */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3), + /* GPP_E19: GPP_E19_PMC_I2C_SDA */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), + /* GPP_E20: GPP_E20_PMC_I2C_SCL */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + /* GPP_E21: I2C_PMC_PD_INT_N */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + /* GPP_E22: THC0_SPI1_DSYNC */ + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF3), + + + /* GPP_F */ + /* GPP_F0: M.2_CNV_BRI_DT_BT_UART2_RTS_N */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* GPP_F1: M.2_CNV_BRI_RSP_BT_UART2_RXD */ + PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), + /* GPP_F2: M.2_CNV_RGI_DT_BT_UART2_TXD */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + /* GPP_F3: M.2_CNV_RGI_RSP_BT_UART2_CTS_N */ + PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), + /* GPP_F4: CNV_RF_RESET_R_N */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + /* GPP_F5: CRF_CLKREQ_R */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), + /* GPP_F6: WLAN_WWAN_COEX3 */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + /* GPP_F7: CRD2_IMGCLKOUT_2 */ + PAD_CFG_NF(GPP_F7, NONE, DEEP, NF2), + /* GPP_F8: CRD3_IMGCLKOUT_3 */ + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF2), + /* GPP_F9: ISH_INT_GP11_LCH */ + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF4), + /* GPP_F10: X1_PCIE_SLOT1_WAKE_N */ + PAD_CFG_GPI_SCI(GPP_F10, NONE, DEEP, LEVEL, INVERT), + /* GPP_F11: NC */ + PAD_NC(GPP_F11, NONE), + /* GPP_F12: THC_I2C1_SCL_TCH_PAD */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* GPP_F13: THC_I2C1_SDA_TCH_PAD */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* GPP_F14: NC */ + PAD_NC(GPP_F14, NONE), + /* GPP_F15: NC */ + PAD_NC(GPP_F15, NONE), + /* GPP_F16: TCH_PAD_PWR_EN */ + PAD_CFG_GPO(GPP_F16, 1, PLTRST), + /* GPP_F17: NC */ + PAD_NC(GPP_F17, NONE), + /* GPP_F18: THC1_INT_N_TCH_PAD */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF3), + /* GPP_F19: CRD2_PRIVACY_LED */ + PAD_CFG_GPO(GPP_F19, 1, PLTRST), + /* GPP_F20: CRD2_RST_N */ + PAD_CFG_GPO(GPP_F20, 1, PLTRST), + /* GPP_F21: NC */ + PAD_NC(GPP_F21, NONE), + /* GPP_F22: NC */ + PAD_NC(GPP_F22, NONE), + /* GPP_F23: TCH_PNL2_PWR_EN */ + PAD_CFG_GPO(GPP_F23, 1, PLTRST), + + /* GPP_H */ + /* GPP_H0: CRD3_RST_N */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + /* GPP_H1: CRD1_PWREN_LCH_IRQ */ + PAD_CFG_GPO(GPP_H1, 1, PLTRST), + /* GPP_H2: WLAN_RST_N */ + PAD_CFG_GPO(GPP_H2, 1, PLTRST), + /* GPP_H3: COINLESS_SPI_NOR_CLEAR */ + PAD_CFG_GPI(GPP_H3, NONE, PLTRST), + /* GPP_H4: CNV_MFUART2_RXD */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF2), + /* GPP_H5: CNV_MFUART2_TXD */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF2), + /* GPP_H6: I2C3_SDA_PSS */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* GPP_H7: I2C3_SCL_PSS */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /*GPP_H8 : UART0_RXD */ + /* PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),*/ + /* GPP_H9 : UART0_TXD */ + /* PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),*/ + /* GPP_H10 : UART0_RTS_B */ + /* PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),*/ + /* GPP_H11 : UART0_CTS_B */ + /* PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),*/ + /* GPP_H12: NC */ + PAD_NC(GPP_H12, NONE), + /* GPP_H13 : CPU_C10_GATE_N_R */ + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + /* GPP_H14 : ISH_I3C1_SDA_SNSR_HDR_R */ + PAD_CFG_NF(GPP_H14, NONE, DEEP, NF4), + /* GPP_H15 : ISH_I3C1_SCL_SNSR_HDR_R */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF4), + /* GPP_H16: CRD1_PRIVACY_LED */ + PAD_CFG_GPO(GPP_H16, 1, PLTRST), + /* GPP_H17: NC */ + PAD_NC(GPP_H17, NONE), + /* GPP_H19 : I2C0_SDA_I3C0_SDA_CSI */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + /* GPP_H20 : I2C0_SCL_I3C0_SCL_CSI */ + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + /* GPP_H21 : I2C1_SDA_CSI_CRD2 */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* GPP_H22 : I2C1_SCL_CSI_CRD2 */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + + /* GPP_S */ + /* GPP_S0: SNDW0_CLK_R */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF6), + /* GPP_S1: SNDW0_DATA_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF6), + /* GPP_S2: SNDW1_CLK_DMIC_CLK_A_0 */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF6), + /* GPP_S3: SNDW1_DATA_DMIC_DATA_0 */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF6), + /* GPP_S4: SNDW2_CLK_R */ + PAD_CFG_GPI_INT(GPP_S4, NONE, PLTRST, EDGE_BOTH), + /* GPP_S5: EN_SPKR_PA */ + PAD_CFG_GPO(GPP_S5, 1, DEEP), + /* GPP_S6: SOC_DMIC1_SNDW3_CLK */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF3), + /* GPP_S7: SOC_DMIC1_SNDW3_DATA */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF3), + + /* GPP_V */ + /* GPP_V0: PM_BATLOW_N */ + PAD_CFG_NF(GPP_V0, NONE, DEEP, NF1), + /* GPP_V1: BC_ACOK_MCP */ + PAD_CFG_NF(GPP_V1, NONE, DEEP, NF1), + /* GPP_V2: LANWAKE_N_R */ + PAD_CFG_NF(GPP_V2, NONE, DEEP, NF1), + /* GPP_V3: PWRBTN_MCP_N */ + PAD_CFG_NF(GPP_V3, NONE, DEEP, NF1), + /* GPP_V4: PM_SLP_S3_N */ + PAD_CFG_NF(GPP_V4, NONE, DEEP, NF1), + /* GPP_V5: PM_SLP_S4_N */ + PAD_CFG_NF(GPP_V5, NONE, DEEP, NF1), + /* GPP_V6: PM_SLP_A_N */ + PAD_CFG_NF(GPP_V6, NONE, DEEP, NF1), + /* GPP_V7: SUS_CLK_LCH */ + PAD_CFG_NF(GPP_V7, NONE, DEEP, NF1), + /* GPP_V8: SLP_WLAN_N */ + PAD_CFG_NF(GPP_V8, NONE, DEEP, NF1), + /* GPP_V9: PM_SLP_S5_N */ + PAD_CFG_NF(GPP_V9, NONE, DEEP, NF1), + /* GPP_V10: LANPHYPC_R_N */ + PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), + /* GPP_V11: PM_SLP_LAN_N */ + PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), + /* GPP_V12: WAKE_N */ + PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), + /* GPP_V13: GPP_V13_CATERR_N */ + PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1), + /* GPP_V14: H_PROCHOT_N */ + PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), + /* GPP_V15: GPP_V15_THERMTRIP_N */ + PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1), + /* GPP_V16: VCCST_EN */ + PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1), + /* GPP_V17: NC */ + PAD_NC(GPP_V17, NONE), +}; + +void variant_configure_gpio_pads(void) +{ + uint8_t board_id = get_board_id(); + + switch (board_id) { + case LNLM_LP5_RVP: + printk(BIOS_DEBUG, "configuring LNLM RVP gpios\n"); + gpio_configure_pads(lnlmrvp_gpio_table, ARRAY_SIZE(lnlmrvp_gpio_table)); + break; + default: + printk(BIOS_DEBUG, "bypass gpios configuration\n"); + } +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), +}; +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/intel/lnl_dev/variants/lnlrvp/memory.c b/src/mainboard/intel/lnl_dev/variants/lnlrvp/memory.c new file mode 100644 index 0000000..3055bb7 --- /dev/null +++ b/src/mainboard/intel/lnl_dev/variants/lnlrvp/memory.c @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <soc/romstage.h> +#include <baseboard/board_id.h> +#include <baseboard/variants.h> + +static const struct mb_cfg lp5_mem_config = { + .type = MEM_TYPE_LP5X, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 8, 9, 11, 10, 13, 12, 15, 14, }, + .dq1 = { 2, 1, 0, 3, 4, 5, 7, 6 }, + }, + .ddr1 = { + .dq0 = { 0, 1, 3, 2, 4, 5, 6, 7, }, + .dq1 = { 15, 13, 14, 12, 11, 10, 9, 8 }, + }, + .ddr2 = { + .dq0 = { 8, 9, 11, 10, 12, 13, 15, 14, }, + .dq1 = { 6, 7, 4, 5, 2, 3, 1, 0 }, + }, + .ddr3 = { + .dq0 = { 10, 11, 9, 8, 14, 12, 13, 15, }, + .dq1 = { 5, 7, 6, 4, 3, 1, 0, 2 }, + }, + .ddr4 = { + .dq0 = { 8, 9, 11, 10, 13, 12, 14, 15, }, + .dq1 = { 2, 1, 0, 3, 4, 5, 7, 6 }, + }, + .ddr5 = { + .dq0 = { 0, 5, 3, 1, 2, 6, 4, 7, }, + .dq1 = { 15, 14, 13, 12, 11, 10, 9, 8,}, + }, + .ddr6 = { + .dq0 = { 14, 13, 15, 12, 8, 11, 10, 9, }, + .dq1 = { 6, 7, 4, 5, 2, 1, 3, 0 }, + }, + .ddr7 = { + .dq0 = { 0, 3, 1, 2, 5, 4, 6, 7, }, + .dq1 = { 9, 10, 11, 8, 12, 15, 14, 13 }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr3 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 } + }, + + .ect = false, /* Early Command Training */ + + .LpDdrDqDqsReTraining = 1, + + .UserBd = BOARD_TYPE_MOBILE, + + .lp5x_config = { + .ccc_config = 0xA2, + }, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + int board_id = get_board_id(); + + switch (board_id) { + case LNLM_LP5_RVP: + return &lp5_mem_config; + default: + die("Unknown board id = 0x%x\n", board_id); + break; + } +}