[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso/psp_verstage: Implement get_uart_base

[Raul Rangel (Code Review)]

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held.
Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61608 )

Change subject: soc/amd/picasso/psp_verstage: Implement get_uart_base
......................................................................

soc/amd/picasso/psp_verstage: Implement get_uart_base

The Picasso PSP doesn't support mapping the UART, so add a dummy
function to return NULL.

BUG=b:215599230
TEST=Build and boot morphius

Signed-off-by: Raul E Rangel 
Change-Id: Ie1f033ff86ebb0f755a9a0b6ff293aa3c8bbbeb6
---
M src/soc/amd/picasso/psp_verstage/Makefile.inc
A src/soc/amd/picasso/psp_verstage/uart.c
2 files changed, 12 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/61608/1

diff --git a/src/soc/amd/picasso/psp_verstage/Makefile.inc b/src/soc/amd/picasso/psp_verstage/Makefile.inc
index 41296c9..82d8efa 100644
--- a/src/soc/amd/picasso/psp_verstage/Makefile.inc
+++ b/src/soc/amd/picasso/psp_verstage/Makefile.inc
@@ -5,6 +5,7 @@

verstage-y += svc.c
 verstage-y += chipset.c
+verstage-y += uart.c

verstage-y += $(top)/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_startup.S
 verstage-y += $(top)/src/vendorcode/amd/fsp/picasso/bl_uapp/bl_uapp_end.S
diff --git a/src/soc/amd/picasso/psp_verstage/uart.c b/src/soc/amd/picasso/psp_verstage/uart.c
new file mode 100644
index 0000000..1c89f10
--- /dev/null
+++ b/src/soc/amd/picasso/psp_verstage/uart.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bl_uapp/bl_syscall_public.h>
+#include <amdblocks/uart.h>
+#include <types.h>
+
+uintptr_t get_uart_base(unsigned int idx)
+{
+	/* Mapping the UART is not supported. */
+	return 0;
+}