[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/common/block/gpio: Add gpio_pm_configure() function

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32788

Change subject: soc/intel/common/block/gpio: Add gpio_pm_configure() function
......................................................................

soc/intel/common/block/gpio: Add gpio_pm_configure() function

This patch adds new function to perform gpio power management
programming as per EDS.

Logic is to enable gpio pm registers as GPDLCGEN, GPDPCGEN, GPRTCDLCGEN,
GPRCOMPCDLCGEN if !CONFIG_SOC_INTEL_DISABLE_DYNAMIC_CLOCK_LOCAL_GATING and
GPSIDEDPCGEN for GPIO communities.

BUG=b:130764684
TEST=Able to build and boot from fixed media on ICL and CML.

Change-Id: I816a70ad92595f013740a235a9799912ad51665e
Signed-off-by: Subrata Banik 
---
M src/soc/intel/common/block/gpio/Kconfig
M src/soc/intel/common/block/gpio/gpio.c
M src/soc/intel/common/block/include/intelblocks/gpio.h
3 files changed, 52 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/32788/1

diff --git a/src/soc/intel/common/block/gpio/Kconfig b/src/soc/intel/common/block/gpio/Kconfig
index bdbc323..30e61d4 100644
--- a/src/soc/intel/common/block/gpio/Kconfig
+++ b/src/soc/intel/common/block/gpio/Kconfig
@@ -43,3 +43,8 @@
    depends on SOC_INTEL_COMMON_BLOCK_GPIO
    bool
    default n
+
+config SOC_INTEL_DISABLE_DYNAMIC_CLOCK_LOCAL_GATING
+	depends on SOC_INTEL_COMMON_BLOCK_GPIO
+	bool
+	default n
diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c
index 3a0594c..7fdf084 100644
--- a/src/soc/intel/common/block/gpio/gpio.c
+++ b/src/soc/intel/common/block/gpio/gpio.c
@@ -57,6 +57,11 @@
 #define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT)
 #define MISCCFG_GPE0_DW2_SHIFT 16
 #define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT)
+#define MISCCFG_GPSIDEDPCGEN 0x20
+#define MISCCFG_GPRCOMPCDLCGEN 0x10
+#define MISCCFG_GPRTCDLCGEN 0x8
+#define MISCCFG_GPDPCGEN 0x2
+#define MISCCFG_GPDLCGEN 0x1

#define GPI_SMI_STS_OFFSET(comm, group) ((comm)->gpi_smi_sts_reg_0 +	\
    			((group) * sizeof(uint32_t)))
@@ -609,3 +614,36 @@
    	}
    }
 }
+
+/*
+ * The function performs GPIO Power Management programming.
+ *
+ * Enable GPDLCGEN, GPDPCGEN, GPRTCDLCGEN,
+ * GPRCOMPCDLCGEN if !CONFIG_SOC_INTEL_DISABLE_DYNAMIC_CLOCK_LOCAL_GATING and
+ * GPSIDEDPCGEN for GPIO communities.
+ */
+void gpio_pm_configure(void)
+{
+	int i;
+	uint32_t misccfg_mask;
+	uint32_t misccfg_value;
+	size_t gpio_communities;
+	const struct pad_community *comm;
+
+	if (CONFIG(SOC_INTEL_DISABLE_DYNAMIC_CLOCK_LOCAL_GATING))
+		misccfg_mask = ~MISCCFG_GPRCOMPCDLCGEN;
+	else
+		misccfg_mask = ~0;
+
+	if (!CONFIG(SOC_INTEL_DISABLE_DYNAMIC_CLOCK_LOCAL_GATING))
+		misccfg_value = MISCCFG_GPRCOMPCDLCGEN;
+
+	misccfg_value |= (MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN |
+			MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN);
+
+	comm = soc_gpio_get_community(&gpio_communities);
+	/* Program GPIO_MISCCFG */
+	for (i = 0; i < gpio_communities; i++, comm++)
+		pcr_rmw32(comm->port, GPIO_MISCCFG,
+				misccfg_mask, misccfg_value);
+}
diff --git a/src/soc/intel/common/block/include/intelblocks/gpio.h b/src/soc/intel/common/block/include/intelblocks/gpio.h
index 4179293..1630e5d 100644
--- a/src/soc/intel/common/block/include/intelblocks/gpio.h
+++ b/src/soc/intel/common/block/include/intelblocks/gpio.h
@@ -215,5 +215,14 @@
  */
 void gpi_clear_int_cfg(void);

+/*
+ * The function performs GPIO Power Management programming.
+ *
+ * Enable GPDLCGEN, GPDPCGEN, GPRTCDLCGEN,
+ * GPRCOMPCDLCGEN if !CONFIG_SOC_INTEL_DISABLE_DYNAMIC_CLOCK_LOCAL_GATING and
+ * GPSIDEDPCGEN for GPIO communities.
+ */
+void gpio_pm_configure(void);
+
 #endif
 #endif /* _SOC_INTELBLOCKS_GPIO_H_ */