[coreboot-gerrit] Change in coreboot[master]: soc/amd/cezanne: Add PCI IRQ Router definitions

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50451 )

Change subject: soc/amd/cezanne: Add PCI IRQ Router definitions
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Patch Set 2:

(1 comment)

File src/soc/amd/cezanne/include/soc/amd_pci_int_defs.h:

https://review.coreboot.org/c/coreboot/+/50451/comment/c54df3bf_dc554e82 
PS1, Line 61: #define PIRQ_UART2	0x78	/* UART2 */
            : #define PIRQ_UART3	0x79	/* UART3 */
> I'm using 56569-A1 Rev 3. […]

oh, turns out that i didn't hit submit on that change request; at least i don't find a confirmation email. in rev 3.01 at least in the memory mapping tables there are only uart0 and uart1 and i'm pretty sure that 2 and 3 don't exist in cezanne