[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1En

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41383 )

Change subject: soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1En
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Patch Set 6:

(2 comments)

https://review.coreboot.org/c/coreboot/+/41383/6/src/soc/intel/tigerlake/rom... 
File src/soc/intel/tigerlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/41383/6/src/soc/intel/tigerlake/rom... 
PS6, Line 119: config->TcssDma0En
I don't think you need a separate chip config for this. You can simply use SA_DEVFN_TCSS_DMA0 and dev->enabled.

https://review.coreboot.org/c/coreboot/+/41383/6/src/soc/intel/tigerlake/rom... 
PS6, Line 120: TcssDma1En
Same here. Use SA_DEVFN_TCSS_DMA1.