[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8192: Do memory pll init before calibration

[CK HU (Code Review)]

Hello Duan huayang,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/44702

to review the following change.

Change subject: soc/mediatek/mt8192: Do memory pll init before calibration
......................................................................

soc/mediatek/mt8192: Do memory pll init before calibration

Signed-off-by: Huayang Duan 
Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6
---
M src/soc/mediatek/mt8192/dramc_pi_main.c
1 file changed, 31 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44702/1

diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c
index e2c7500..c36ff43 100644
--- a/src/soc/mediatek/mt8192/dramc_pi_main.c
+++ b/src/soc/mediatek/mt8192/dramc_pi_main.c
@@ -2,6 +2,8 @@

#include <soc/dramc_pi_api.h>
 #include <soc/dramc_register.h>
+#include <soc/pll.h>
+#include <soc/pll_common.h>
 #include <soc/mt6359p.h>

static void set_vcore_voltage_for_each_freq(const struct ddr_cali *cali)
@@ -16,6 +18,34 @@
 {
 }

+static void mem_pll_init(void)
+{
+	unsigned int tmp;
+
+	write32(&mtk_apmixed->mpll_con3, 0x3);
+
+	udelay(30);
+	tmp = read32(&mtk_apmixed->mpll_con3);
+	write32(&mtk_apmixed->mpll_con3, tmp & 0xfffffffd);
+
+	udelay(1);
+	write32(&mtk_apmixed->mpll_con1, 0x84200000);
+	tmp = read32(&mtk_apmixed->mpll_con0);
+	write32(&mtk_apmixed->mpll_con0, tmp | 0x1);
+
+	udelay(20);
+	tmp = read32(&mtk_apmixed->pllon_con0);
+	write32(&mtk_apmixed->pllon_con0, tmp & ~(0x1 << 2));
+	tmp = read32(&mtk_apmixed->pllon_con0);
+	write32(&mtk_apmixed->pllon_con0, tmp & ~(0x1 << 11));
+	tmp = read32(&mtk_apmixed->pllon_con1);
+	write32(&mtk_apmixed->pllon_con1, tmp & ~(0x1 << 20));
+	tmp = read32(&mtk_apmixed->pllon_con2);
+	write32(&mtk_apmixed->pllon_con2, tmp & ~(0x1 << 2));
+	tmp = read32(&mtk_apmixed->pllon_con3);
+	write32(&mtk_apmixed->pllon_con3, tmp & ~(0x1 << 2));
+}
+
 void init_dram(const struct dramc_data *dparam)
 {
    u32 bc_bak;
@@ -35,6 +65,7 @@
    cali.emi_config = &ddr_info->emi_config;

dramc_set_broadcast(DRAMC_BROADCAST_ON);
+	mem_pll_init();

global_option_init(&cali);
    bc_bak = dramc_get_broadcast();