[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block/cse: Clear post code before reset

[Duncan Laurie (Code Review)]

Duncan Laurie has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47257 )

Change subject: soc/intel/common/block/cse: Clear post code before reset
......................................................................

soc/intel/common/block/cse: Clear post code before reset

To avoid "unknown post code 0x55" entries in the event log on cold boot
clear the post code before doing the CSE initiated reset.

Signed-off-by: Duncan Laurie 
Change-Id: I68078c04230dbc24f9cc63b1ef5c435055aa1186
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47257
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
Reviewed-by: Tim Wawrzynczak 
---
M src/soc/intel/common/block/cse/cse.c
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index ef6db3d..d10492b 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -555,6 +555,9 @@
 {
    uint32_t csr;

+	/* Clear post code to prevent eventlog entry from unknown code. */
+	post_code(0);
+
    /* Send reset request */
    csr = read_host_csr();
    csr |= (CSR_RESET | CSR_IG);