[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/pantherlake: Bind SoC config VR settings to respective UPD

[Subrata Banik (Code Review)]

Attention is currently required from: Intel coreboot Reviewers, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N.

Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85131?usp=email )

Change subject: soc/intel/pantherlake: Bind SoC config VR settings to respective UPD
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Patch Set 13:

(1 comment)

Patchset:

PS6:
> We probably can find common ground, but that would mean using the lowest common denominator, which to my understanding might undermine the performances. I would think we do not want to go that route.
>
> `b001`, `b004`, and `b00a` are from the Panther Lake H12Xe family, while `b002` is from the PTL H4Xe family. These two families have different IA, GT, and SA  I_TRIP_NOM values. If a variant needs to support both families, I need to introduce some software architectural changes. Could you tell me if you have a variant that supports both families?

do you want to push this CL as base for CB:86622 ?

btw, in absence of devicetree override these UPDs would be set as zero aka disable . do you see any risk ?