6 Apr
2021
6 Apr
'21
5:23 a.m.
Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans, Michael Niewöhner, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52110 )
Change subject: mb/hp/280_g2/romstage.c: Correct CaVrefConfig setting ......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52110/comment/17aab61f_08b31cb8 PS1, Line 9: With DDR4, CA Vref goes to channel 0, and CH1 Vref goes to channel 1. Sorry, I do not fully grasp the explanation. If it’s related to DDR4, why can’t FSP detect it’s FSP and set the correct setting itself?
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I64606824b4f82affb0fcfc78e68ba29859a1cc69
Gerrit-Change-Number: 52110
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