Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans, Michael Niewöhner, Patrick Rudolph.
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1 comment:
Commit Message:
Patch Set #1, Line 9: With DDR4, CA Vref goes to channel 0, and CH1 Vref goes to channel 1.
Sorry, I do not fully grasp the explanation. If it’s related to DDR4, why can’t FSP detect it’s FSP and set the correct setting itself?
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Gerrit-Change-Id: I64606824b4f82affb0fcfc78e68ba29859a1cc69
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