Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50611 )
Change subject: ChromeOS: Use CHROMEOS_NVS guard ......................................................................
ChromeOS: Use CHROMEOS_NVS guard
Replace CONFIG(CHROMEOS) with CONFIG(CHROMEOS_NVS) for cases where the conditional and dependency are clearly about the presence of an ACPI NVS table specified by vendorcode. For couple locations also CONFIG(HAVE_ACPI_TABLES) changes to CONFIG(CHROMEOS_NVS).
This also helps find some of the CONFIG(CHROMEOS) cases that might be more FMAP and VPD related and not about ChromeOS per-se, as suggested by followup works.
Change-Id: Ife888ae43093949bb2d3e397565033037396f434 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/50611 Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/acpi/Makefile.inc M src/acpi/acpigen_extern.asl M src/acpi/dsdt_top.asl M src/acpi/gnvs.c M src/arch/x86/smbios.c M src/mainboard/google/butterfly/acpi_tables.c M src/mainboard/google/parrot/acpi_tables.c M src/mainboard/google/stout/acpi_tables.c M src/mainboard/samsung/lumpy/acpi_tables.c M src/soc/intel/broadwell/pch/me.c M src/southbridge/intel/bd82x6x/me_common.c M src/southbridge/intel/lynxpoint/me.c M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/Makefile.inc M src/vendorcode/google/chromeos/ramoops.c 15 files changed, 21 insertions(+), 16 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Lance Zhao: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/acpi/Makefile.inc b/src/acpi/Makefile.inc index b8e4422..3c3bd9e 100644 --- a/src/acpi/Makefile.inc +++ b/src/acpi/Makefile.inc @@ -10,7 +10,7 @@ ramstage-y += acpigen_ps2_keybd.c ramstage-y += acpigen_usb.c ramstage-y += device.c -ramstage-$(CONFIG_CHROMEOS) += chromeos-gnvs.c +ramstage-$(CONFIG_CHROMEOS_NVS) += chromeos-gnvs.c ramstage-$(CONFIG_ACPI_SOC_NVS) += gnvs.c ramstage-y += pld.c ramstage-y += sata.c diff --git a/src/acpi/acpigen_extern.asl b/src/acpi/acpigen_extern.asl index 5e380b5..117177e 100644 --- a/src/acpi/acpigen_extern.asl +++ b/src/acpi/acpigen_extern.asl @@ -19,7 +19,7 @@ OperationRegion (DNVS, SystemMemory, NVB1, NVS1) #endif
-#if CONFIG(CHROMEOS) +#if CONFIG(CHROMEOS_NVS) External (NVB2, IntObj) External (NVS2, IntObj) OperationRegion (CNVS, SystemMemory, NVB2, NVS2) diff --git a/src/acpi/dsdt_top.asl b/src/acpi/dsdt_top.asl index eece7f7..ff148ae 100644 --- a/src/acpi/dsdt_top.asl +++ b/src/acpi/dsdt_top.asl @@ -2,7 +2,7 @@
#include <acpi/acpigen_extern.asl>
-#if CONFIG(CHROMEOS) +#if CONFIG(CHROMEOS_NVS) /* Chrome OS specific */ #include <vendorcode/google/chromeos/acpi/gnvs.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl> diff --git a/src/acpi/gnvs.c b/src/acpi/gnvs.c index 01aff62..3decebb 100644 --- a/src/acpi/gnvs.c +++ b/src/acpi/gnvs.c @@ -26,7 +26,7 @@ gnvs_size = 0x100; if (CONFIG(ACPI_HAS_DEVICE_NVS)) gnvs_size = 0x2000; - else if (CONFIG(CHROMEOS)) + else if (CONFIG(CHROMEOS_NVS)) gnvs_size = 0x1000;
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, gnvs_size); @@ -38,7 +38,7 @@ if (CONFIG(CONSOLE_CBMEM)) gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE);
- if (CONFIG(CHROMEOS)) + if (CONFIG(CHROMEOS_NVS)) gnvs_assign_chromeos((u8 *)gnvs + GNVS_CHROMEOS_ACPI_OFFSET); }
@@ -78,7 +78,7 @@ acpigen_write_name_dword("NVS0", 0x100); acpigen_pop_len();
- if (CONFIG(CHROMEOS)) { + if (CONFIG(CHROMEOS_NVS)) { acpigen_write_scope("\"); acpigen_write_name_dword("NVB2", (uintptr_t)gnvs + GNVS_CHROMEOS_ACPI_OFFSET); acpigen_write_name_dword("NVS2", 0xf00); diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 33ab1ba..a48cf43 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -390,7 +390,7 @@ t->vendor = smbios_add_string(t->eos, "coreboot"); t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date);
- if (CONFIG(CHROMEOS) && CONFIG(HAVE_ACPI_TABLES)) { + if (CONFIG(CHROMEOS_NVS)) { uintptr_t version_address = (uintptr_t)t->eos; /* SMBIOS offsets start at 1 rather than 0 */ version_address += (u32)smbios_string_table_len(t->eos) - 1; diff --git a/src/mainboard/google/butterfly/acpi_tables.c b/src/mainboard/google/butterfly/acpi_tables.c index 29faea3..c3324aa 100644 --- a/src/mainboard/google/butterfly/acpi_tables.c +++ b/src/mainboard/google/butterfly/acpi_tables.c @@ -18,7 +18,7 @@ // The firmware read/write status is a "virtual" switch and // will be handled elsewhere. Until then hard-code to // read/write instead of read-only for developer mode. - if (CONFIG(CHROMEOS)) + if (CONFIG(CHROMEOS_NVS)) gnvs_set_ecfw_rw();
// the lid is open by default. diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index 1cb4597..535edb8 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -21,7 +21,7 @@ gnvs->s5u0 = 0; gnvs->s5u1 = 0;
- if (CONFIG(CHROMEOS) && !parrot_ec_running_ro()) + if (CONFIG(CHROMEOS_NVS) && !parrot_ec_running_ro()) gnvs_set_ecfw_rw();
/* EC handles all active thermal and fan control on Parrot. */ diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c index fe12e30..19549af 100644 --- a/src/mainboard/google/stout/acpi_tables.c +++ b/src/mainboard/google/stout/acpi_tables.c @@ -22,7 +22,7 @@ gnvs->s5u0 = 0; gnvs->s5u1 = 0;
- if (CONFIG(CHROMEOS) && !get_recovery_mode_switch()) + if (CONFIG(CHROMEOS_NVS) && !get_recovery_mode_switch()) gnvs_set_ecfw_rw();
/* EC handles all thermal and fan control on Stout. */ diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c index c697457..282ba34 100644 --- a/src/mainboard/samsung/lumpy/acpi_tables.c +++ b/src/mainboard/samsung/lumpy/acpi_tables.c @@ -44,6 +44,6 @@ gnvs->tmax = MAX_TEMPERATURE; gnvs->flvl = 5;
- if (CONFIG(CHROMEOS) && ec_read(0xcb)) + if (CONFIG(CHROMEOS_NVS) && ec_read(0xcb)) gnvs_set_ecfw_rw(); } diff --git a/src/soc/intel/broadwell/pch/me.c b/src/soc/intel/broadwell/pch/me.c index 88d2172..6c01f07 100644 --- a/src/soc/intel/broadwell/pch/me.c +++ b/src/soc/intel/broadwell/pch/me.c @@ -770,7 +770,7 @@ printk(BIOS_DEBUG, "\n");
/* Save hash in NVS for the OS to verify */ - if (CONFIG(CHROMEOS)) + if (CONFIG(CHROMEOS_NVS)) chromeos_set_me_hash(extend, count);
return 0; diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c index 1c6899d..177d581 100644 --- a/src/southbridge/intel/bd82x6x/me_common.c +++ b/src/southbridge/intel/bd82x6x/me_common.c @@ -396,7 +396,7 @@ printk(BIOS_DEBUG, "\n");
/* Save hash in NVS for the OS to verify */ - if (CONFIG(CHROMEOS)) + if (CONFIG(CHROMEOS_NVS)) chromeos_set_me_hash(extend, count);
return 0; diff --git a/src/southbridge/intel/lynxpoint/me.c b/src/southbridge/intel/lynxpoint/me.c index b028c63..886fd90 100644 --- a/src/southbridge/intel/lynxpoint/me.c +++ b/src/southbridge/intel/lynxpoint/me.c @@ -730,7 +730,7 @@ printk(BIOS_DEBUG, "\n");
/* Save hash in NVS for the OS to verify */ - if (CONFIG(CHROMEOS)) + if (CONFIG(CHROMEOS_NVS)) chromeos_set_me_hash(extend, count);
return 0; diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index e81f31d..e6d45e1 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -12,6 +12,7 @@ select ELOG if BOOT_DEVICE_SUPPORTS_WRITES select COLLECT_TIMESTAMPS select VBOOT + select CHROMEOS_NVS if ACPI_SOC_NVS select VPD select VBOOT_SLOTS_RW_AB help @@ -87,5 +88,9 @@ Some boards declare the DRAM part number in the CBI instead of the SPD. This option allows those boards to declare that their DRAM part number is stored in the CBI.
+config CHROMEOS_NVS + bool + depends on ACPI_SOC_NVS + endif # CHROMEOS endmenu diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index ba00d77..c05d8e7 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -1,7 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only
ramstage-$(CONFIG_ELOG) += elog.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += gnvs.c +ramstage-$(CONFIG_CHROMEOS_NVS) += gnvs.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c ramstage-y += vpd_mac.c vpd_serialno.c vpd_calibration.c diff --git a/src/vendorcode/google/chromeos/ramoops.c b/src/vendorcode/google/chromeos/ramoops.c index 77e079f..3b658b7 100644 --- a/src/vendorcode/google/chromeos/ramoops.c +++ b/src/vendorcode/google/chromeos/ramoops.c @@ -38,7 +38,7 @@ return; }
- if (CONFIG(HAVE_ACPI_TABLES)) + if (CONFIG(CHROMEOS_NVS)) set_ramoops(ram_oops, size); }