Attention is currently required from: Rob Barnes, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58638 )
Change subject: mb/google/guybrush: Move GSC_SOC_INT_L from GPIO_3 to GPIO_85 ......................................................................
Patch Set 1: Code-Review+2
(2 comments)
File src/mainboard/google/guybrush/variants/guybrush/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/58638/comment/ee8049b1_bcd1198a PS1, Line 162: e
We dont need to specify alias again. Actually it led to devicetree compilation error.
Ack
File src/mainboard/google/guybrush/variants/nipperkin/gpio.c:
https://review.coreboot.org/c/coreboot/+/58638/comment/85da7892_01a9c0f3 PS1, Line 40: BID == 1: GSC_SOC_INT_L, BID > 1: Unused
These GPIOs are set up in verstage before ESPI is setup. […]
Yeah, we would need to split the config into two, the Native Function pins and the GPIO pins. i.e., eSPI+I2C+PCIe Reset+UART, and then the rest.
verstage_mainboard_early_init could handle configuring the NF pins, then verstage_soc_init can setup eSPI. After that then verstage_mainboard_init would handle configuring the rest of the GPIOs.
I'm fine skipping this for now.