Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43087 )
Change subject: mb/bostentech: Add GBYT4 port ......................................................................
Patch Set 27: Code-Review+1
(5 comments)
https://review.coreboot.org/c/coreboot/+/43087/27//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43087/27//COMMIT_MSG@9 PS27, Line 9: - Single channel DDR3L: requires mrc.bin (extracted from ChromeBook firmware) Please wrap lines around at 72 characters
https://review.coreboot.org/c/coreboot/+/43087/27//COMMIT_MSG@16 PS27, Line 16: ITE8728F nit: IT8728F
https://review.coreboot.org/c/coreboot/+/43087/27//COMMIT_MSG@20 PS27, Line 20: #43133 CB:43133
https://review.coreboot.org/c/coreboot/+/43087/27/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/43087/27/src/mainboard/bostentech/g... PS27, Line 83: spurious tab?
https://review.coreboot.org/c/coreboot/+/43087/27/src/mainboard/bostentech/g... File src/mainboard/bostentech/gbyt4/romstage.c:
https://review.coreboot.org/c/coreboot/+/43087/27/src/mainboard/bostentech/g... PS27, Line 13: : /* NOTE: SPD must be read manually as mrc.bin's SMBus support is broken */ : enable_smbus(); : i2c_eeprom_read(0x50, 0, sizeof(spd_buf), spd_buf); Could we have this workaround in common code? If dram_info_location is set to SMBUS, then read the SPDs into an array.