[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge: Encapsulate JEDEC write leveling

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47617 )

Change subject: nb/intel/sandybridge: Encapsulate JEDEC write leveling
......................................................................

nb/intel/sandybridge: Encapsulate JEDEC write leveling

Create and rename a few functions to contain the entire JEDEC write
leveling algorithm. Not all write training is JEDEC write leveling.

Tested on Asus P8H61-M PRO, still boots.

Change-Id: Ie9c6315340164029e30354723b4103d906633602
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/sandybridge/raminit_common.c
1 file changed, 19 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/47617/1

diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index cff7e8b..2799103 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -1714,7 +1714,7 @@
    }
 }

-static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank)
+static int write_level_rank(ramctr_timing *ctrl, int channel, int slotrank)
 {
    int timB;
    int statistics[NUM_LANES][128];
@@ -1960,13 +1960,9 @@
  * the DRAM-chip samples the CLK on every DQS edge and feeds back the sampled value on the data
  * lanes (DQ).
  */
-int write_training(ramctr_timing *ctrl)
+static int jedec_write_leveling(ramctr_timing *ctrl)
 {
-	int channel, slotrank, lane;
-	int err;
-
-	FOR_ALL_POPULATED_CHANNELS
-		MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27);
+	int channel, slotrank;

disable_refresh_machine(ctrl);

@@ -1989,7 +1985,7 @@

/* Set any valid value for timB, it gets corrected later */
    FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
-		err = discover_timB(ctrl, channel, slotrank);
+		const int err = write_level_rank(ctrl, channel, slotrank);
    	if (err)
    		return err;
    }
@@ -2021,6 +2017,21 @@

toggle_io_reset();

+	return 0;
+}
+
+int write_training(ramctr_timing *ctrl)
+{
+	int channel, slotrank, lane;
+	int err;
+
+	FOR_ALL_POPULATED_CHANNELS
+		MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27);
+
+	err = jedec_write_leveling(ctrl);
+	if (err)
+		return err;
+
    printram("CPE\n");
    precharge(ctrl);
    printram("CPF\n");