Hello Shaunak Saha, build bot (Jenkins), Wonkyu Kim, Raj Astekar, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39317
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: Enable CNVi Mode ......................................................................
soc/intel/tigerlake: Enable CNVi Mode
Add configs to enable CNVi mode and CNViBtCore.
BUG=none BRANCH=none TEST=Build and boot tglrvp
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Ic372348a1409b2594a85b71b2fc742be96b84b87 --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params_tgl.c 2 files changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/39317/2