[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp/cpx: Add multi-core init

[Maxim Polyakov (Code Review)]

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40035 )

Change subject: soc/intel/xeon_sp/cpx: Add multi-core init
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Patch Set 7: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/40035/7/src/soc/intel/xeon_sp/cpx/c... 
File src/soc/intel/xeon_sp/cpx/cpu.c:

https://review.coreboot.org/c/coreboot/+/40035/7/src/soc/intel/xeon_sp/cpx/c... 
PS7, Line 82: intel_microcode_load_unlocked
> yeah this is a valid concern. However I believe this "phase 1" is taking place in FSP-T. […]

Well, however, we have to be careful with cache manipulations, since functions from the common cpu initialization code may not take into account the specifics of the CPX + fsp platform and use the cache incorrectly.