[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Add CrashLog implementation for intel TGL

[Francois Toguo Fotso (Code Review)]

Attention is currently required from: Francois Toguo Fotso, Martin Roth, Tim Wawrzynczak, Duncan Laurie, Patrick Rudolph.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Tim Wawrzynczak, Duncan Laurie, Tim Wawrzynczak, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/49943

to look at the new patch set (#10).

Change subject: soc/intel/tigerlake: Add CrashLog implementation for intel TGL
......................................................................

soc/intel/tigerlake: Add CrashLog implementation for intel TGL

CrashLog is a diagnostic feature for Intel TGL based platforms.
It is meant to capture the state of the platform before a crash.
The state of relevant registers is preserved across a warm reset.

BUG=None
TEST=CrashLog data generated, extracted, processed, decoded sucessfully on delbin.

Signed-off-by: Francois Toguo 
Change-Id: Ie3763cebcd1178709cc8597710bf062a30901809
---
M src/soc/intel/common/block/include/intelblocks/pmc_ipc.h
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/Makefile.inc
M src/soc/intel/tigerlake/acpi.c
A src/soc/intel/tigerlake/crashlog_lib.c
A src/soc/intel/tigerlake/include/soc/crashlog_def.h
A src/soc/intel/tigerlake/include/soc/crashlog_lib.h
M src/soc/intel/tigerlake/include/soc/iomap.h
M src/soc/intel/tigerlake/include/soc/pci_devs.h
M src/soc/intel/tigerlake/romstage/fsp_params.c
M src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
11 files changed, 927 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/49943/10