Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47990 )
Change subject: soc/intel/common/fast_spi: Add extended decode window support ......................................................................
Patch Set 5:
(5 comments)
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... File src/soc/intel/common/block/fast_spi/fast_spi.c:
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... PS4, Line 14: #include <soc/pcr_ids.h>
Not required any more. This file doesn't use the SPI DMI macro directly. […]
Done
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... PS4, Line 272: biod
nit: BIOS
Done
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... PS4, Line 327: fast_spi_enable_ext_bios
Actually, GPMR will be programmed before disabling PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY so that i […]
Should we change the document to reflect this ?
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... File src/soc/intel/common/block/fast_spi/fast_spi_def.h:
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... PS4, Line 21: BIT(27)
(1 << 27) just to keep it consistent with other definitions here.
Done
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... File src/soc/intel/common/block/include/intelblocks/fast_spi.h:
https://review.coreboot.org/c/coreboot/+/47990/4/src/soc/intel/common/block/... PS4, Line 82: /* : * SOC function to get SPI-DMI Destination Id : */
Since this is a single line comment, […]
I tried to keep it consistent with other single line comments in this file For example Line 69, 73 etc. I can change it to single line if you still want me to.