Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34752 )
Change subject: arch/x86: Attempt to boot without postcar stage/phase ......................................................................
Patch Set 6:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34752/6/src/arch/x86/c_start.S File src/arch/x86/c_start.S:
https://review.coreboot.org/c/coreboot/+/34752/6/src/arch/x86/c_start.S@19 PS6, Line 19: #endif Can't this be included below at line 45 unconditionally? That was my suggestion. I was also curious if we could define the same symbol twice w/o the assembler complaining. Also the RAMSTAGE_X86_64 is still incompatible with LOADS_FROM_ROMSTAGE on cache as ram employed devices.
https://review.coreboot.org/c/coreboot/+/34752/6/src/arch/x86/exit_car.S File src/arch/x86/exit_car.S:
https://review.coreboot.org/c/coreboot/+/34752/6/src/arch/x86/exit_car.S@37 PS6, Line 37: Incase in case
https://review.coreboot.org/c/coreboot/+/34752/6/src/arch/x86/exit_car.S@38 PS6, Line 38: * be handled inside c_start.S hence avoiding dual GDT programming here We'd be reliant on the descriptor cache. If a select is loaded before the ram backed gdt is enabled we would be in trouble. I think it's important to comment on the assumptions.
https://review.coreboot.org/c/coreboot/+/34752/6/src/arch/x86/include/arch/c... File src/arch/x86/include/arch/cpu.h:
https://review.coreboot.org/c/coreboot/+/34752/6/src/arch/x86/include/arch/c... PS6, Line 355: unnecessary edit