Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger.
Hello Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/73497
to look at the new patch set (#2).
Change subject: soc/amd/stoneyridge/romstage: pass C state control IO base address ......................................................................
soc/amd/stoneyridge/romstage: pass C state control IO base address
Instead of hoping that the default the C state control IO address in binaryPI won't interfere with any other IO space usage in coreboot, assign the ACPI_CSTATE_CONTROL value to the CStateIoBaseAddress platform config structure element to make sure that binaryPI will use a known address for the IO port based C state control. binaryPI will write this address to the MSR_CSTATE_ADDRESS and will then also use these IO ports in the _CST packages in the PSTATE SSDT, so changing this won't cause a mismatch between those two.
The default CStateIoBaseAddress in the FT4 Stoneyridge binaryPI used on Careena is 0x1770, so this didn't collide with any other IO space registers, but it's still much better to tell binaryPI which exact IO addresses to use.
TEST=On Careena MSR_CSTATE_ADDRESS now contains the ACPI_CSTATE_CONTROL IO base address 0x420 and the PSTATE SSDT has the IO address 0x421 in the _CST package entry for the second C state which are both the expected values.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I207202802427d4bf00f283bcbd83a174ab0a2846 --- M src/soc/amd/stoneyridge/include/soc/iomap.h M src/soc/amd/stoneyridge/romstage.c 2 files changed, 35 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/73497/2