[coreboot-gerrit] Change in coreboot[master]: sb/intel/bd82x6x: Rework PCH ID cache

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49168 )

Change subject: sb/intel/bd82x6x: Rework PCH ID cache
......................................................................

sb/intel/bd82x6x: Rework PCH ID cache

Work around a romstage restriction. Globals (or static variables) cannot
be initialized to a non-zero value because there's no data section. Note
that the revision ID for stepping A0 is zero, so `pch_silicon_revision`
will no longer use the cached value for this PCH stepping. Since it is a
pre-production stepping, it is most likely not used anywhere anymore.

Change-Id: I07663d151cbc2d2ed7e4813bf870de52848753fd
Signed-off-by: Angel Pons 
---
M src/southbridge/intel/bd82x6x/common.c
1 file changed, 4 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/49168/1

diff --git a/src/southbridge/intel/bd82x6x/common.c b/src/southbridge/intel/bd82x6x/common.c
index 7480174..0094db6 100644
--- a/src/southbridge/intel/bd82x6x/common.c
+++ b/src/southbridge/intel/bd82x6x/common.c
@@ -13,9 +13,9 @@

int pch_silicon_revision(void)
 {
-	static int pch_revision_id = -1;
+	static int pch_revision_id = 0;

-	if (pch_revision_id < 0)
+	if (!pch_revision_id)
    	pch_revision_id = pci_read_config8(PCH_LPC_DEV,	PCI_REVISION_ID);

return pch_revision_id;
@@ -23,9 +23,9 @@

int pch_silicon_type(void)
 {
-	static int pch_type = -1;
+	static int pch_type = 0;

-	if (pch_type < 0)
+	if (!pch_type)
    	pch_type = pci_read_config8(PCH_LPC_DEV, PCI_DEVICE_ID + 1);

return pch_type;