[coreboot-gerrit] Change in coreboot[master]: amd/padmelon: Add fintek superio to devicetree

[John E. Kabat (Code Review)]

Hello Marshall Dawson,

I'd like you to do a code review. Please visit

https://review.coreboot.org/21038

to review the following change.

Change subject: amd/padmelon: Add fintek superio to devicetree
......................................................................

amd/padmelon: Add fintek superio to devicetree

Add the path to the device and enable the two UARTs.  Leave
other devices disabled.

Change-Id: I73d128d5fa4227c05fcebe1ed2a3ac98b4923426
Signed-off-by: Marshall Dawson 
---
M src/mainboard/amd/padmelon/devicetree.cb
1 file changed, 19 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/21038/1

diff --git a/src/mainboard/amd/padmelon/devicetree.cb b/src/mainboard/amd/padmelon/devicetree.cb
index 5c107e2..2b6171a 100644
--- a/src/mainboard/amd/padmelon/devicetree.cb
+++ b/src/mainboard/amd/padmelon/devicetree.cb
@@ -52,7 +52,25 @@
    				end
    			end # SM
    			#device pci 14.2 on  end # HDA	0x4383
-				device pci 14.3 on  end # LPC	0x439d
+				device pci 14.3 on      # LPC	0x439d
+					chip superio/fintek/f81803a
+						register "conf_key_mode" = "0x77"
+						device pnp 4e.1 on      # COM1
+							io 0x60 = 0x3f8
+							irq 0x70 = 4
+						end
+						device pnp 4e.2 on      # COM2
+							io 0x60 = 0x2f8
+							irq 0x70 = 3
+						end
+						device pnp 4e.4 off end	# HWM
+						device pnp 4e.5 off end	# KBC
+						device pnp 4e.6 off end # GPIO
+						device pnp 4e.7 off end # WDT
+						device pnp 4e.a off end # PME
+						
+					end # f81803a
+				end # LPC
    			device pci 14.7 on  end # SD
    		end	#chip southbridge/amd/pi/hudson