Martin Roth has uploaded this change for review. ( https://review.coreboot.org/28906
Change subject: mb/google/kahlee: Set 100MHz fast spi read for supported boards ......................................................................
mb/google/kahlee: Set 100MHz fast spi read for supported boards
BUG=b:116737547 TEST=Boot Careena, look at signal on a scope.
Change-Id: I9ad95c858376ad0e6c9e787055d3fa72b5682191 Signed-off-by: Martin Roth martinroth@chromium.org --- M src/mainboard/google/kahlee/bootblock/bootblock.c 1 file changed, 31 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/28906/1
diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index 8531fc0..40fd390 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -14,6 +14,7 @@ */
#include <baseboard/variants.h> +#include <boardid.h> #include <bootblock_common.h> #include <soc/gpio.h> #include <soc/southbridge.h> @@ -32,34 +33,49 @@ sb_program_gpios(gpios, num_gpios); }
+/* Use 100MHz on on boards that can support it */ +static int set_100mhz_fast_read(void) +{ + uint32_t id = board_id(); + if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CAREENA) && (id <= 2 || id >= 5)) + return 1; + + return 0; +} + void bootblock_mainboard_init(void) { + uint16_t normal = SPI_SPEED_33M; + uint16_t fast = SPI_SPEED_66M; + uint16_t altio = SPI_SPEED_66M; + + /* + * W25Q128FW Setup + * Normal Read 40MHz + * Fast Read 104MHz + * Dual Read IO (1-2-2) + */ + if (IS_ENABLED(CONFIG_EM100)) { /* * We should be able to rely on defaults, but it seems safer * to explicitly set up these registers. */ sb_read_mode(SPI_READ_MODE_NOM); - sb_set_spi100(SPI_SPEED_16M, /* Normal */ - SPI_SPEED_16M, /* Fast */ - SPI_SPEED_16M, /* AltIO */ - SPI_SPEED_66M); /* TPM */ + + normal = SPI_SPEED_16M; + fast = SPI_SPEED_16M; + altio = SPI_SPEED_16M; } else { - /* - * W25Q128FW Setup - * Normal Read 40MHz - * Fast Read 104MHz - * Dual Read IO (1-2-2) - */ sb_read_mode(SPI_READ_MODE_DUAL122);
- /* Set SPI speeds before verstage. Needed for TPM */ - sb_set_spi100(SPI_SPEED_33M, /* Normal */ - SPI_SPEED_66M, /* Fast */ - SPI_SPEED_66M, /* AltIO */ - SPI_SPEED_66M); /* TPM */ + if (set_100mhz_fast_read()) + fast = SPI_SPEED_100M; }
+ /* Normal, Fast, AltIO, TPM */ + sb_set_spi100(normal, fast, altio, SPI_SPEED_66M); + /* Setup TPM decode before verstage */ sb_tpm_decode_spi(); }