[coreboot-gerrit] Change in coreboot[master]: mb/intel/tglrvp: Enable Hybrid storage mode

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39233 )

Change subject: mb/intel/tglrvp: Enable Hybrid storage mode
......................................................................

mb/intel/tglrvp: Enable Hybrid storage mode

BUG=b:148604250
BRANCH=none
TEST=Build and test booting TGLRVP form NVMe and Optane
Check PCIe lane configuration
Show all the NVMe devices
lspci -d ::0108
Show all the NVMe devices and be really verbose
lspci -vvvd ::0108
Print PCIe lane capabilities and configurations for all the NVMe devices.
lspci -vvvd ::0108 | grep -e x[124]
Print all the PCIe information of the device ae:00.0
lspci -vvvs ae:

Signed-off-by: Wonkyu Kim 
Change-Id: I5fc8fa0897ad006de9ebe20115bf3033e1e1b499
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39233
Tested-by: build bot (Jenkins) 
Reviewed-by: Caveh Jalali 
Reviewed-by: Srinidhi N Kaushik 
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
2 files changed, 6 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Srinidhi N Kaushik: Looks good to me, approved
  Caveh Jalali: Looks good to me, but someone else must approve
  Wonkyu Kim: Looks good to me, but someone else must approve

diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index e60e648..4492acb 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -37,6 +37,9 @@
    register "PcieRpEnable[8]" = "1"
    register "PcieRpEnable[10]" = "1"

+	# Hybrid storage mode
+	register "HybridStorageMode" = "1"
+
    register "PcieClkSrcClkReq[1]" = "1"
    register "PcieClkSrcClkReq[2]" = "2"
    register "PcieClkSrcClkReq[3]" = "3"
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index 1f05e0e..643db36 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -37,6 +37,9 @@
    register "PcieRpEnable[8]" = "1"
    register "PcieRpEnable[10]" = "1"

+	# Hybrid storage mode
+	register "HybridStorageMode" = "1"
+
    register "PcieClkSrcClkReq[1]" = "1"
    register "PcieClkSrcClkReq[2]" = "2"
    register "PcieClkSrcClkReq[3]" = "3"