Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45054 )
Change subject: soc/amd/picasso: fix tsc_freq_mhz ......................................................................
soc/amd/picasso: fix tsc_freq_mhz
According to Core::X86::Msr::PStateDef explanation from PPR 55570, cpufid is bit[7:0] and cpudid is bit[13:8]. And correct calcuation based on the same section.
Signed-off-by: Kangheui Won khwon@chromium.org Change-Id: Ia225c9d4fedc5097c8861eae73ca81c9cc344fe5 --- M src/soc/amd/picasso/tsc_freq.c 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/45054/1
diff --git a/src/soc/amd/picasso/tsc_freq.c b/src/soc/amd/picasso/tsc_freq.c index a86080c..c3dd000 100644 --- a/src/soc/amd/picasso/tsc_freq.c +++ b/src/soc/amd/picasso/tsc_freq.c @@ -22,9 +22,9 @@ if (!(msr.hi & 0x80000000)) die("Unknown error: cannot determine P-state 0\n");
- cpufid = (msr.lo & 0x3f); - cpudid = (msr.lo & 0x1c0) >> 6; + cpufid = (msr.lo & 0xff); + cpudid = (msr.lo & 0x3f00) >> 8;
- mhz = (100 * (cpufid + 0x10)) / (0x01 << cpudid); + mhz = (200 * cpufid) / cpudid; return mhz; }