Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55063 )
Change subject: src: Use initial_lapicid() instead of open coding it ......................................................................
src: Use initial_lapicid() instead of open coding it
Since initial_lapicid() returns an unsigned int, change the type of the local variables the return value gets assigned to to unsigned int as well if applicable. Also change the printk format strings for printing the variable's contents to %u where it was %d before.
Change-Id: I289015b81b2a9d915c4cab9b0544fc19b85df7a3 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/55063 Reviewed-by: Raul Rangel rrangel@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/drivers/amd/agesa/eventlog.c M src/drivers/amd/agesa/romstage.c M src/soc/amd/picasso/mca.c M src/soc/amd/stoneyridge/mca.c M src/soc/intel/xeon_sp/smmrelocate.c 5 files changed, 13 insertions(+), 14 deletions(-)
Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved
diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c index 49ab4ce..126a2ee 100644 --- a/src/drivers/amd/agesa/eventlog.c +++ b/src/drivers/amd/agesa/eventlog.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <cpu/x86/lapic.h> #include <console/console.h> #include <stdint.h> #include <string.h> @@ -97,7 +98,7 @@ { int i;
- task->apic_id = (u8) (cpuid_ebx(1) >> 24); + task->apic_id = (u8)initial_lapicid(); task->func = func; task->function_name = undefined;
diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index 29423ef..b8f38ce 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -6,6 +6,7 @@ #include <arch/romstage.h> #include <cbmem.h> #include <console/console.h> +#include <cpu/x86/lapic.h> #include <halt.h> #include <program_loading.h> #include <romstage_handoff.h> @@ -35,7 +36,7 @@ struct postcar_frame pcf; struct sysinfo romstage_state; struct sysinfo *cb = &romstage_state; - u8 initial_apic_id = (u8) (cpuid_ebx(1) >> 24); + unsigned int initial_apic_id = initial_lapicid(); int cbmem_initted = 0;
fill_sysinfo(cb); @@ -49,7 +50,7 @@ console_init(); }
- printk(BIOS_DEBUG, "APIC %02d: CPU Family_Model = %08x\n", + printk(BIOS_DEBUG, "APIC %02u: CPU Family_Model = %08x\n", initial_apic_id, cpuid_eax(1));
set_ap_entry_ptr(ap_romstage_main); diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index acb248d..65b1916 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -2,6 +2,7 @@
#include <amdblocks/msr_zen.h> #include <amdblocks/reset.h> +#include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> #include <acpi/acpi.h> #include <soc/cpu.h> @@ -160,10 +161,8 @@ for (i = 0 ; i < num_banks ; i++) { mci.sts = rdmsr(MCAX_STATUS_MSR(i)); if (mci.sts.hi || mci.sts.lo) { - int core = cpuid_ebx(1) >> 24; - - printk(BIOS_WARNING, "#MC Error: core %d, bank %d %s\n", - core, i, + printk(BIOS_WARNING, "#MC Error: core %u, bank %d %s\n", + initial_lapicid(), i, i < ARRAY_SIZE(mca_bank_name) ? mca_bank_name[i] : "");
printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n", diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index db5fabc3..1523563 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/reset.h> +#include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> #include <acpi/acpi.h> #include <soc/cpu.h> @@ -163,10 +164,8 @@
mci.sts = rdmsr(IA32_MC0_STATUS + (i * 4)); if (mci.sts.hi || mci.sts.lo) { - int core = cpuid_ebx(1) >> 24; - - printk(BIOS_WARNING, "#MC Error: core %d, bank %d %s\n", - core, i, mca_bank_name[i]); + printk(BIOS_WARNING, "#MC Error: core %u, bank %d %s\n", + initial_lapicid(), i, mca_bank_name[i]);
printk(BIOS_WARNING, " MC%d_STATUS = %08x_%08x\n", i, mci.sts.hi, mci.sts.lo); diff --git a/src/soc/intel/xeon_sp/smmrelocate.c b/src/soc/intel/xeon_sp/smmrelocate.c index dc4b511..f44fc62 100644 --- a/src/soc/intel/xeon_sp/smmrelocate.c +++ b/src/soc/intel/xeon_sp/smmrelocate.c @@ -2,6 +2,7 @@
#include <assert.h> #include <string.h> +#include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/intel/em64t101_save_state.h> #include <cpu/intel/smm_reloc.h> @@ -86,7 +87,6 @@ { u32 smbase; u32 iedbase; - int apic_id; em64t101_smm_state_save_area_t *save_state; /* * The relocated handler runs with all CPUs concurrently. Therefore @@ -96,9 +96,8 @@ smbase = staggered_smbase; iedbase = relo_params->ied_base;
- apic_id = cpuid_ebx(1) >> 24; printk(BIOS_DEBUG, "New SMBASE=0x%08x IEDBASE=0x%08x\n apic_id=0x%x\n", - smbase, iedbase, apic_id); + smbase, iedbase, initial_lapicid());
save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state));