Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45930 )
Change subject: soc/intel/common/block/systemagent/memmap.c: Align cached region ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45930/2/src/soc/intel/common/block/... File src/soc/intel/common/block/systemagent/memmap.c:
https://review.coreboot.org/c/coreboot/+/45930/2/src/soc/intel/common/block/... PS2, Line 70: postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); Compared to older versions, we don't care about the space above `cbmem_top` as TSEG is cached separately below. So how about aligning up to 8MiB and then subtracting 16MiB? It should give better results (more DRAM covered that we care about) in case `cbmem_top` is already aligned.