Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35031 )
Change subject: soc/intel/skylake: Add Lewisburg PCH GPIOs support ......................................................................
soc/intel/skylake: Add Lewisburg PCH GPIOs support
The pin layout in this patch corresponds to the driver in the linux kernel for Lewisburg PCH GPIO hardware [1]
[1] drivers/pinctrl/intel/pinctrl-lewisburg.c
These changes are in accordance with the documentation: [*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US
Change-Id: Ia72c37121fa9616e4ef0ce4acfb36188363c231e Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/gpio.c M src/soc/intel/skylake/include/soc/gpio_defs.h A src/soc/intel/skylake/include/soc/gpio_wlb_pch_defs.h M src/soc/intel/skylake/include/soc/pcr_ids.h 5 files changed, 440 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/35031/1
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 13c1517..34fd97c 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -175,6 +175,12 @@ help Choose this option if you have a PCH-H chipset.
+config WELISBURG_SOC_PCH_H + bool + default n + help + Choose this option if you have the Lewisburg C62x PCH chipset. + config NHLT_DMIC_2CH bool default n diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 67edeae..0130936 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -36,6 +36,9 @@ static const struct pad_group skl_community_com0_groups[] = { INTEL_GPP(GPP_A0, GPP_A0, GPP_A23), /* GPP A */ INTEL_GPP(GPP_A0, GPP_B0, GPP_B23), /* GPP B */ +#if CONFIG(WELISBURG_SOC_PCH_H) + INTEL_GPP(GPP_A0, GPP_F0, GPP_F23), /* GPP F */ +#endif };
static const struct pad_group skl_community_com1_groups[] = { @@ -48,19 +51,38 @@ INTEL_GPP(GPP_C0, GPP_H0, GPP_H23), /* GPP H */ #else INTEL_GPP(GPP_C0, GPP_D0, GPP_D23), /* GPP D */ +# if CONFIG(WELISBURG_SOC_PCH_H) + INTEL_GPP(GPP_C0, GPP_E0, GPP_E12), /* GPP E */ +# else INTEL_GPP(GPP_C0, GPP_E0, GPP_E23), /* GPP E */ +# endif #endif };
static const struct pad_group skl_community_com3_groups[] = { #if CONFIG(SKYLAKE_SOC_PCH_H) INTEL_GPP(GPP_I0, GPP_I0, GPP_I10), /* GPP I */ +#elif CONFIG(WELISBURG_SOC_PCH_H) + INTEL_GPP(GPP_I0, GPP_I0, RCOMP_3P3), /* GPP I */ #else INTEL_GPP(GPP_F0, GPP_F0, GPP_F23), /* GPP F */ INTEL_GPP(GPP_F0, GPP_G0, GPP_G7), /* GPP G */ #endif };
+#if CONFIG(WELISBURG_SOC_PCH_H) +static const struct pad_group skl_community_com4_groups[] = { + INTEL_GPP(GPP_J0, GPP_J0, GPP_J23), /* GPP F */ + INTEL_GPP(GPP_J0, GPP_K0, RCOMP_1P8_3P3), /* GPP G */ +}; + +static const struct pad_group skl_community_com5_groups[] = { + INTEL_GPP(GPP_J0, GPP_G0, GPP_G23), /* GPP G */ + INTEL_GPP(GPP_J0, GPP_H0, GPP_H23), /* GPP H */ + INTEL_GPP(GPP_J0, GPP_L2, GPP_L19), /* GPP L */ +}; +#endif + static const struct pad_group skl_community_com2_groups[] = { INTEL_GPP(GPD0, GPD0, GPD11), /* GPP GDP */ }; @@ -69,7 +91,11 @@ { .port = PID_GPIOCOM0, .first_pad = GPP_A0, +#if CONFIG(WELISBURG_SOC_PCH_H) + .last_pad = GPP_F23, +#else .last_pad = GPP_B23, +#endif .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, @@ -89,6 +115,8 @@ .first_pad = GPP_C0, #if CONFIG(SKYLAKE_SOC_PCH_H) .last_pad = GPP_H23, +#elif CONFIG(WELISBURG_SOC_PCH_H) + .last_pad = GPP_E12, #else .last_pad = GPP_E23, #endif @@ -108,7 +136,7 @@ .num_groups = ARRAY_SIZE(skl_community_com1_groups), }, { .port = PID_GPIOCOM3, -#if CONFIG(SKYLAKE_SOC_PCH_H) +#if CONFIG(SKYLAKE_SOC_PCH_H) || CONFIG(WELISBURG_SOC_PCH_H) .first_pad = GPP_I0, .last_pad = GPP_I10, #else @@ -130,6 +158,44 @@ .groups = skl_community_com3_groups, .num_groups = ARRAY_SIZE(skl_community_com3_groups), }, { +#if CONFIG(WELISBURG_SOC_PCH_H) + .port = PID_GPIOCOM4, + .first_pad = GPP_J0, + .last_pad = GPP_K10, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPIO_COM4", + .acpi_path = "\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = skl_community_com4_groups, + .num_groups = ARRAY_SIZE(skl_community_com4_groups), + }, { + .port = PID_GPIOCOM4, + .first_pad = GPP_G0, + .last_pad = GPP_L19, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPIO_COM4", + .acpi_path = "\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = skl_community_com5_groups, + .num_groups = ARRAY_SIZE(skl_community_com5_groups), + }, { +#endif .port = PID_GPIOCOM2, .first_pad = GPD0, .last_pad = GPD11, @@ -161,17 +227,27 @@ static const struct pmc_to_gpio_route routes[] = { { GPP_A, GPP_A}, { GPP_B, GPP_B}, +#if CONFIG(WELISBURG_SOC_PCH_H) + { GPP_F, GPP_F}, +#endif { GPP_C, GPP_C}, { GPP_D, GPP_D}, { GPP_E, GPP_E}, +#if CONFIG(WELISBURG_SOC_PCH_H) + { GPP_I, GPP_I}, + { GPP_J, GPP_J}, + { GPP_K, GPP_K}, +#else { GPP_F, GPP_F}, { GPP_G, GPP_G}, -#if CONFIG(SKYLAKE_SOC_PCH_H) +# if CONFIG(SKYLAKE_SOC_PCH_H) { GPP_H, GPP_H}, { GPP_I, GPP_I}, +# endif #endif { GPD, GPD}, }; + *num = ARRAY_SIZE(routes); return routes; } @@ -179,7 +255,7 @@ uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg, int dw_reg, uint32_t reg_val) { - if (CONFIG(SKYLAKE_SOC_PCH_H)) + if (CONFIG(SKYLAKE_SOC_PCH_H) || CONFIG(WELISBURG_SOC_PCH_H)) return reg_val; /* * For U/Y series, clear PAD_CFG1_TOL_1V8 in GPP_F4 diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 321d3c2..0285989 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -20,6 +20,8 @@ #endif #if CONFIG(SKYLAKE_SOC_PCH_H) # include <soc/gpio_pch_h_defs.h> +#elif CONFIG(WELISBURG_SOC_PCH_H) +# include <soc/gpio_wlb_pch_defs.h> #else # include <soc/gpio_soc_defs.h> #endif @@ -33,6 +35,22 @@ #define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) #define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) #define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS) +#if CONFIG(WELISBURG_SOC_PCH_H) +# define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) +# define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) +#endif + +#if CONFIG(WELISBURG_SOC_PCH_H) + +#define NUM_GPI_STATUS_REGS \ + ((NUM_GPIO_COM0_GPI_REGS) +\ + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM3_GPI_REGS) +\ + (NUM_GPIO_COM4_GPI_REGS) +\ + (NUM_GPIO_COM5_GPI_REGS) +\ + (NUM_GPIO_COM2_GPI_REGS) +\ + +#else
#define NUM_GPI_STATUS_REGS \ ((NUM_GPIO_COM0_GPI_REGS) +\ @@ -218,6 +236,8 @@ #define GPD10_IRQ 0x5a #define GPD11_IRQ 0x5b
+#endif + /* Register defines. */ #define GPIO_MISCCFG 0x10 #define GPIO_DRIVER_IRQ_ROUTE_MASK 8 diff --git a/src/soc/intel/skylake/include/soc/gpio_wlb_pch_defs.h b/src/soc/intel/skylake/include/soc/gpio_wlb_pch_defs.h new file mode 100644 index 0000000..636837c --- /dev/null +++ b/src/soc/intel/skylake/include/soc/gpio_wlb_pch_defs.h @@ -0,0 +1,333 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_GPIO_WLB_PCH_DEFS_H_ +#define _SOC_GPIO_WLB_PCH_DEFS_H_ + +/* GPIO Community 0 */ +#define GPP_A 0x0 +#define GPP_B 0x1 +#define GPP_F 0x2 +/* GPIO Community 1 */ +#define GPP_C 0x3 +#define GPP_D 0x4 +#define GPP_E 0x5 +/* GPIO Community 3 */ +#define GPP_I 0x6 +/* GPIO Community 4 */ +#define GPP_J 0x7 +#define GPP_K 0x8 +/* GPIO Community 5 */ +#define GPP_G 0x9 +#define GPP_H 0xA +#define GPP_L 0xB +/* GPIO Community 2 */ +#define GPD 0xC + +#define GPIO_NUM_GROUPS 13 +#define GPIO_MAX_NUM_PER_GROUP 24 + +/* Group A */ +#define GPP_A0 0 +#define GPP_A1 1 +#define GPP_A2 2 +#define GPP_A3 3 +#define GPP_A4 4 +#define GPP_A5 5 +#define GPP_A6 6 +#define GPP_A7 7 +#define GPP_A8 8 +#define GPP_A9 9 +#define GPP_A10 10 +#define GPP_A11 11 +#define GPP_A12 12 +#define GPP_A13 13 +#define GPP_A14 14 +#define GPP_A15 15 +#define GPP_A16 16 +#define GPP_A17 17 +#define GPP_A18 18 +#define GPP_A19 19 +#define GPP_A20 20 +#define GPP_A21 21 +#define GPP_A22 22 +#define GPP_A23 23 +/* Group B */ +#define GPP_B0 24 +#define GPP_B1 25 +#define GPP_B2 26 +#define GPP_B3 27 +#define GPP_B4 28 +#define GPP_B5 29 +#define GPP_B6 30 +#define GPP_B7 31 +#define GPP_B8 32 +#define GPP_B9 33 +#define GPP_B10 34 +#define GPP_B11 35 +#define GPP_B12 36 +#define GPP_B13 37 +#define GPP_B14 38 +#define GPP_B15 39 +#define GPP_B16 40 +#define GPP_B17 41 +#define GPP_B18 42 +#define GPP_B19 43 +#define GPP_B20 44 +#define GPP_B21 45 +#define GPP_B22 46 +#define GPP_B23 47 +/* Group F */ +#define GPP_F0 48 +#define GPP_F1 49 +#define GPP_F2 50 +#define GPP_F3 51 +#define GPP_F4 52 +#define GPP_F5 53 +#define GPP_F6 54 +#define GPP_F7 55 +#define GPP_F8 56 +#define GPP_F9 57 +#define GPP_F10 58 +#define GPP_F11 59 +#define GPP_F12 60 +#define GPP_F13 61 +#define GPP_F14 62 +#define GPP_F15 63 +#define GPP_F16 64 +#define GPP_F17 65 +#define GPP_F18 66 +#define GPP_F19 67 +#define GPP_F20 68 +#define GPP_F21 69 +#define GPP_F22 70 +#define GPP_F23 71 + +#define NUM_GPIO_COM0_PADS (GPP_F23 - GPP_A0 + 1) + +/* Group C */ +#define GPP_C0 72 +#define GPP_C1 73 +#define GPP_C2 74 +#define GPP_C3 75 +#define GPP_C4 76 +#define GPP_C5 77 +#define GPP_C6 78 +#define GPP_C7 79 +#define GPP_C8 80 +#define GPP_C9 81 +#define GPP_C10 82 +#define GPP_C11 83 +#define GPP_C12 84 +#define GPP_C13 85 +#define GPP_C14 86 +#define GPP_C15 87 +#define GPP_C16 88 +#define GPP_C17 89 +#define GPP_C18 90 +#define GPP_C19 91 +#define GPP_C20 92 +#define GPP_C21 93 +#define GPP_C22 94 +#define GPP_C23 95 +/* Group D */ +#define GPP_D0 96 +#define GPP_D1 97 +#define GPP_D2 98 +#define GPP_D3 99 +#define GPP_D4 100 +#define GPP_D5 101 +#define GPP_D6 102 +#define GPP_D7 103 +#define GPP_D8 104 +#define GPP_D9 105 +#define GPP_D10 106 +#define GPP_D11 107 +#define GPP_D12 108 +#define GPP_D13 109 +#define GPP_D14 110 +#define GPP_D15 111 +#define GPP_D16 112 +#define GPP_D17 113 +#define GPP_D18 114 +#define GPP_D19 115 +#define GPP_D20 116 +#define GPP_D21 117 +#define GPP_D22 118 +#define GPP_D23 119 +/* Group E */ +#define GPP_E0 120 +#define GPP_E1 121 +#define GPP_E2 122 +#define GPP_E3 123 +#define GPP_E4 124 +#define GPP_E5 125 +#define GPP_E6 126 +#define GPP_E7 127 +#define GPP_E8 128 +#define GPP_E9 129 +#define GPP_E10 130 +#define GPP_E11 131 +#define GPP_E12 132 + +#define NUM_GPIO_COM1_PADS (GPP_E12 - GPP_C0 + 1) + +/* Group I */ +#define GPP_I0 133 +#define GPP_I1 134 +#define GPP_I2 135 +#define GPP_I3 136 +#define GPP_I4 137 +#define GPP_I5 138 +#define GPP_I6 139 +#define GPP_I7 140 +#define GPP_I8 141 +#define GPP_I9 142 +#define GPP_I10 143 +#define RCOMP_3P3 144 + +#define NUM_GPIO_COM3_PADS (RCOMP_3P3 - GPP_I0 + 1) + +/* Group J */ +#define GPP_J0 145 +#define GPP_J1 146 +#define GPP_J2 147 +#define GPP_J3 148 +#define GPP_J4 149 +#define GPP_J5 150 +#define GPP_J6 151 +#define GPP_J7 152 +#define GPP_J8 153 +#define GPP_J9 154 +#define GPP_J10 155 +#define GPP_J11 156 +#define GPP_J12 157 +#define GPP_J13 158 +#define GPP_J14 159 +#define GPP_J15 160 +#define GPP_J16 161 +#define GPP_J17 162 +#define GPP_J18 163 +#define GPP_J19 164 +#define GPP_J20 165 +#define GPP_J21 166 +#define GPP_J22 167 +#define GPP_J23 168 +/* Group K */ +#define GPP_K0 169 +#define GPP_K1 170 +#define GPP_K2 171 +#define GPP_K3 172 +#define GPP_K4 173 +#define GPP_K5 174 +#define GPP_K6 175 +#define GPP_K7 176 +#define GPP_K8 177 +#define GPP_K9 178 +#define GPP_K10 179 + +#define RCOMP_1P8_3P3 180 + +#define NUM_GPIO_COM4_PADS (RCOMP_1P8_3P3 - GPP_J0 + 1) + +/* Group G */ +#define GPP_G0 181 +#define GPP_G1 182 +#define GPP_G2 183 +#define GPP_G3 184 +#define GPP_G4 185 +#define GPP_G5 186 +#define GPP_G6 187 +#define GPP_G7 188 +#define GPP_G8 189 +#define GPP_G9 190 +#define GPP_G10 191 +#define GPP_G11 192 +#define GPP_G12 193 +#define GPP_G13 194 +#define GPP_G14 195 +#define GPP_G15 196 +#define GPP_G16 197 +#define GPP_G17 198 +#define GPP_G18 199 +#define GPP_G19 200 +#define GPP_G20 201 +#define GPP_G21 202 +#define GPP_G22 203 +#define GPP_G23 204 +/* Group H */ +#define GPP_H0 205 +#define GPP_H1 206 +#define GPP_H2 207 +#define GPP_H3 208 +#define GPP_H4 209 +#define GPP_H5 210 +#define GPP_H6 211 +#define GPP_H7 212 +#define GPP_H8 213 +#define GPP_H9 214 +#define GPP_H10 215 +#define GPP_H11 216 +#define GPP_H12 217 +#define GPP_H13 218 +#define GPP_H14 219 +#define GPP_H15 220 +#define GPP_H16 221 +#define GPP_H17 222 +#define GPP_H18 223 +#define GPP_H19 224 +#define GPP_H20 225 +#define GPP_H21 226 +#define GPP_H22 227 +#define GPP_H23 228 +/* Group L */ +#define GPP_L2 229 +#define GPP_L3 230 +#define GPP_L4 231 +#define GPP_L5 232 +#define GPP_L6 233 +#define GPP_L7 234 +#define GPP_L8 235 +#define GPP_L9 236 +#define GPP_L10 237 +#define GPP_L11 238 +#define GPP_L12 239 +#define GPP_L13 240 +#define GPP_L14 241 +#define GPP_L15 242 +#define GPP_L16 243 +#define GPP_L17 244 +#define GPP_L18 245 +#define GPP_L19 246 + +#define NUM_GPIO_COM5_PADS (GPP_L23 - GPP_G0 + 1) + +/* Group GPD */ +#define GPD0 247 +#define GPD1 248 +#define GPD2 249 +#define GPD3 250 +#define GPD4 251 +#define GPD5 252 +#define GPD6 253 +#define GPD7 254 +#define GPD8 255 +#define GPD9 256 +#define GPD10 257 +#define GPD11 258 + +#define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1) + +#endif diff --git a/src/soc/intel/skylake/include/soc/pcr_ids.h b/src/soc/intel/skylake/include/soc/pcr_ids.h index 71affd8..1185e17 100644 --- a/src/soc/intel/skylake/include/soc/pcr_ids.h +++ b/src/soc/intel/skylake/include/soc/pcr_ids.h @@ -20,6 +20,8 @@ * Port ids */ #define PID_PSTH 0x89 +#define PID_GPIOCOM5 0x11 +#define PID_GPIOCOM4 0xAB #define PID_GPIOCOM3 0xAC #define PID_GPIOCOM2 0xAD #define PID_GPIOCOM1 0xAE