HAOUAS Elyes (ehaouas@noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6341
-gerrit
commit 344d5144e3c996f77cd52f15f0acdea2dbcf7ea6 Author: Elyes HAOUAS ehaouas@noos.fr Date: Tue Jul 22 19:52:22 2014 +0200
southbridge/intel/bd82x6x: Remove a trailing whitespace
Change-Id: Ica8259c75645d43a5f947e4a3c31071898e9b550 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- src/southbridge/intel/bd82x6x/me.h | 88 +++++++------- src/southbridge/intel/bd82x6x/pch.h | 224 ++++++++++++++++++------------------ 2 files changed, 156 insertions(+), 156 deletions(-)
diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index aaeb24d..c16951f 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -34,37 +34,37 @@ #define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */
#define PCI_ME_HFS 0x40 -#define ME_HFS_CWS_RESET 0 -#define ME_HFS_CWS_INIT 1 -#define ME_HFS_CWS_REC 2 -#define ME_HFS_CWS_NORMAL 5 -#define ME_HFS_CWS_WAIT 6 -#define ME_HFS_CWS_TRANS 7 -#define ME_HFS_CWS_INVALID 8 -#define ME_HFS_STATE_PREBOOT 0 -#define ME_HFS_STATE_M0_UMA 1 -#define ME_HFS_STATE_M3 4 -#define ME_HFS_STATE_M0 5 -#define ME_HFS_STATE_BRINGUP 6 -#define ME_HFS_STATE_ERROR 7 -#define ME_HFS_ERROR_NONE 0 -#define ME_HFS_ERROR_UNCAT 1 -#define ME_HFS_ERROR_IMAGE 3 -#define ME_HFS_ERROR_DEBUG 4 -#define ME_HFS_MODE_NORMAL 0 -#define ME_HFS_MODE_DEBUG 2 -#define ME_HFS_MODE_DIS 3 -#define ME_HFS_MODE_OVER_JMPR 4 -#define ME_HFS_MODE_OVER_MEI 5 -#define ME_HFS_BIOS_DRAM_ACK 1 -#define ME_HFS_ACK_NO_DID 0 -#define ME_HFS_ACK_RESET 1 -#define ME_HFS_ACK_PWR_CYCLE 2 -#define ME_HFS_ACK_S3 3 -#define ME_HFS_ACK_S4 4 -#define ME_HFS_ACK_S5 5 -#define ME_HFS_ACK_GBL_RESET 6 -#define ME_HFS_ACK_CONTINUE 7 +#define ME_HFS_CWS_RESET 0 +#define ME_HFS_CWS_INIT 1 +#define ME_HFS_CWS_REC 2 +#define ME_HFS_CWS_NORMAL 5 +#define ME_HFS_CWS_WAIT 6 +#define ME_HFS_CWS_TRANS 7 +#define ME_HFS_CWS_INVALID 8 +#define ME_HFS_STATE_PREBOOT 0 +#define ME_HFS_STATE_M0_UMA 1 +#define ME_HFS_STATE_M3 4 +#define ME_HFS_STATE_M0 5 +#define ME_HFS_STATE_BRINGUP 6 +#define ME_HFS_STATE_ERROR 7 +#define ME_HFS_ERROR_NONE 0 +#define ME_HFS_ERROR_UNCAT 1 +#define ME_HFS_ERROR_IMAGE 3 +#define ME_HFS_ERROR_DEBUG 4 +#define ME_HFS_MODE_NORMAL 0 +#define ME_HFS_MODE_DEBUG 2 +#define ME_HFS_MODE_DIS 3 +#define ME_HFS_MODE_OVER_JMPR 4 +#define ME_HFS_MODE_OVER_MEI 5 +#define ME_HFS_BIOS_DRAM_ACK 1 +#define ME_HFS_ACK_NO_DID 0 +#define ME_HFS_ACK_RESET 1 +#define ME_HFS_ACK_PWR_CYCLE 2 +#define ME_HFS_ACK_S3 3 +#define ME_HFS_ACK_S4 4 +#define ME_HFS_ACK_S5 5 +#define ME_HFS_ACK_GBL_RESET 6 +#define ME_HFS_ACK_CONTINUE 7
struct me_hfs { u32 working_state: 4; @@ -93,10 +93,10 @@ struct me_uma { } __attribute__ ((packed));
#define PCI_ME_H_GS 0x4c -#define ME_INIT_DONE 1 -#define ME_INIT_STATUS_SUCCESS 0 -#define ME_INIT_STATUS_NOMEM 1 -#define ME_INIT_STATUS_ERROR 2 +#define ME_INIT_DONE 1 +#define ME_INIT_STATUS_SUCCESS 0 +#define ME_INIT_STATUS_NOMEM 1 +#define ME_INIT_STATUS_ERROR 2
struct me_did { u32 uma_base: 16; @@ -106,13 +106,13 @@ struct me_did { } __attribute__ ((packed));
#define PCI_ME_GMES 0x48 -#define ME_GMES_PHASE_ROM 0 -#define ME_GMES_PHASE_BUP 1 -#define ME_GMES_PHASE_UKERNEL 2 -#define ME_GMES_PHASE_POLICY 3 -#define ME_GMES_PHASE_MODULE 4 -#define ME_GMES_PHASE_UNKNOWN 5 -#define ME_GMES_PHASE_HOST 6 +#define ME_GMES_PHASE_ROM 0 +#define ME_GMES_PHASE_BUP 1 +#define ME_GMES_PHASE_UKERNEL 2 +#define ME_GMES_PHASE_POLICY 3 +#define ME_GMES_PHASE_MODULE 4 +#define ME_GMES_PHASE_UNKNOWN 5 +#define ME_GMES_PHASE_HOST 6
struct me_gmes { u32 bist_in_prog : 1; @@ -132,8 +132,8 @@ struct me_gmes { } __attribute__ ((packed));
#define PCI_ME_HERES 0xbc -#define PCI_ME_EXT_SHA1 0x00 -#define PCI_ME_EXT_SHA256 0x02 +#define PCI_ME_EXT_SHA1 0x00 +#define PCI_ME_EXT_SHA256 0x02 #define PCI_ME_HER(x) (0xc0+(4*(x)))
struct me_heres { diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 90de855..86b36cd 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -91,9 +91,9 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define SECSTS 0x1e #define INTR 0x3c #define BCTRL 0x3e -#define SBR (1 << 6) -#define SEE (1 << 1) -#define PERE (1 << 0) +#define SBR (1 << 6) +#define SEE (1 << 1) +#define PERE (1 << 0)
#define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) @@ -109,8 +109,8 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define GEN_PMCON_2 0xa2 #define GEN_PMCON_3 0xa4 #define ETR3 0xac -#define ETR3_CWORWRE (1 << 18) -#define ETR3_CF9GR (1 << 20) +#define ETR3_CWORWRE (1 << 18) +#define ETR3_CF9GR (1 << 20)
/* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) @@ -119,7 +119,7 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer);
#define PMBASE 0x40 #define ACPI_CNTL 0x44 -#define ACPI_EN (1 << 7) +#define ACPI_EN (1 << 7) #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ @@ -136,16 +136,16 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer);
#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ #define LPC_EN 0x82 /* LPC IF Enables Register */ -#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ -#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ -#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ -#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ -#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ -#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ -#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ -#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ -#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ -#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */ +#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ +#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ +#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ +#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ +#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ +#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ +#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ +#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ +#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ +#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */ #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ @@ -157,48 +157,48 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) #define INTR_LN 0x3c #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ -#define IDE_DECODE_ENABLE (1 << 15) -#define IDE_SITRE (1 << 14) -#define IDE_ISP_5_CLOCKS (0 << 12) -#define IDE_ISP_4_CLOCKS (1 << 12) -#define IDE_ISP_3_CLOCKS (2 << 12) -#define IDE_RCT_4_CLOCKS (0 << 8) -#define IDE_RCT_3_CLOCKS (1 << 8) -#define IDE_RCT_2_CLOCKS (2 << 8) -#define IDE_RCT_1_CLOCKS (3 << 8) -#define IDE_DTE1 (1 << 7) -#define IDE_PPE1 (1 << 6) -#define IDE_IE1 (1 << 5) -#define IDE_TIME1 (1 << 4) -#define IDE_DTE0 (1 << 3) -#define IDE_PPE0 (1 << 2) -#define IDE_IE0 (1 << 1) -#define IDE_TIME0 (1 << 0) +#define IDE_DECODE_ENABLE (1 << 15) +#define IDE_SITRE (1 << 14) +#define IDE_ISP_5_CLOCKS (0 << 12) +#define IDE_ISP_4_CLOCKS (1 << 12) +#define IDE_ISP_3_CLOCKS (2 << 12) +#define IDE_RCT_4_CLOCKS (0 << 8) +#define IDE_RCT_3_CLOCKS (1 << 8) +#define IDE_RCT_2_CLOCKS (2 << 8) +#define IDE_RCT_1_CLOCKS (3 << 8) +#define IDE_DTE1 (1 << 7) +#define IDE_PPE1 (1 << 6) +#define IDE_IE1 (1 << 5) +#define IDE_TIME1 (1 << 4) +#define IDE_DTE0 (1 << 3) +#define IDE_PPE0 (1 << 2) +#define IDE_IE0 (1 << 1) +#define IDE_TIME0 (1 << 0) #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ -#define IDE_SSDE1 (1 << 3) -#define IDE_SSDE0 (1 << 2) -#define IDE_PSDE1 (1 << 1) -#define IDE_PSDE0 (1 << 0) +#define IDE_SSDE1 (1 << 3) +#define IDE_SSDE0 (1 << 2) +#define IDE_PSDE1 (1 << 1) +#define IDE_PSDE0 (1 << 0)
#define IDE_SDMA_TIM 0x4a
#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ -#define SIG_MODE_SEC_NORMAL (0 << 18) -#define SIG_MODE_SEC_TRISTATE (1 << 18) -#define SIG_MODE_SEC_DRIVELOW (2 << 18) -#define SIG_MODE_PRI_NORMAL (0 << 16) -#define SIG_MODE_PRI_TRISTATE (1 << 16) -#define SIG_MODE_PRI_DRIVELOW (2 << 16) -#define FAST_SCB1 (1 << 15) -#define FAST_SCB0 (1 << 14) -#define FAST_PCB1 (1 << 13) -#define FAST_PCB0 (1 << 12) -#define SCB1 (1 << 3) -#define SCB0 (1 << 2) -#define PCB1 (1 << 1) -#define PCB0 (1 << 0) +#define SIG_MODE_SEC_NORMAL (0 << 18) +#define SIG_MODE_SEC_TRISTATE (1 << 18) +#define SIG_MODE_SEC_DRIVELOW (2 << 18) +#define SIG_MODE_PRI_NORMAL (0 << 16) +#define SIG_MODE_PRI_TRISTATE (1 << 16) +#define SIG_MODE_PRI_DRIVELOW (2 << 16) +#define FAST_SCB1 (1 << 15) +#define FAST_SCB0 (1 << 14) +#define FAST_PCB1 (1 << 13) +#define FAST_PCB0 (1 << 12) +#define SCB1 (1 << 3) +#define SCB0 (1 << 2) +#define PCB1 (1 << 1) +#define PCB0 (1 << 0)
#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ @@ -336,9 +336,9 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define IOBPIRI 0x2330 #define IOBPD 0x2334 #define IOBPS 0x2338 -#define IOBPS_RW_BX ((1 << 9)|(1 << 10)) -#define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) -#define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10)) +#define IOBPS_RW_BX ((1 << 9)|(1 << 10)) +#define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) +#define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10))
#define D31IP 0x3100 /* 32bit */ #define D31IP_TTIP 24 /* Thermal Throttle Pin */ @@ -437,31 +437,31 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer);
/* ICH7 PMBASE */ #define PM1_STS 0x00 -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define PRBTNOR_STS (1 << 11) -#define RTC_STS (1 << 10) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define BM_STS (1 << 4) -#define TMROF_STS (1 << 0) +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) #define PM1_EN 0x02 -#define PCIEXPWAK_DIS (1 << 14) -#define RTC_EN (1 << 10) -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) -#define TMROF_EN (1 << 0) +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) #define PM1_CNT 0x04 -#define SLP_EN (1 << 13) -#define SLP_TYP (7 << 10) -#define SLP_TYP_S0 0 -#define SLP_TYP_S1 1 -#define SLP_TYP_S3 5 -#define SLP_TYP_S4 6 -#define SLP_TYP_S5 7 -#define GBL_RLS (1 << 2) -#define BM_RLD (1 << 1) -#define SCI_EN (1 << 0) +#define SLP_EN (1 << 13) +#define SLP_TYP (7 << 10) +#define SLP_TYP_S0 0 +#define SLP_TYP_S1 1 +#define SLP_TYP_S3 5 +#define SLP_TYP_S4 6 +#define SLP_TYP_S5 7 +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) #define PM1_TMR 0x08 #define PROC_CNT 0x10 #define LV2 0x14 @@ -469,33 +469,33 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define LV4 0x16 #define PM2_CNT 0x50 // mobile only #define GPE0_STS 0x20 -#define PME_B0_STS (1 << 13) -#define PME_STS (1 << 11) -#define BATLOW_STS (1 << 10) -#define PCI_EXP_STS (1 << 9) -#define RI_STS (1 << 8) -#define SMB_WAK_STS (1 << 7) -#define TCOSCI_STS (1 << 6) -#define SWGPE_STS (1 << 2) -#define HOT_PLUG_STS (1 << 1) +#define PME_B0_STS (1 << 13) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define RI_STS (1 << 8) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) #define GPE0_EN 0x28 -#define PME_B0_EN (1 << 13) -#define PME_EN (1 << 11) -#define TCOSCI_EN (1 << 6) +#define PME_B0_EN (1 << 13) +#define PME_EN (1 << 11) +#define TCOSCI_EN (1 << 6) #define SMI_EN 0x30 -#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic -#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic -#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS -#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) -#define MCSMI_EN (1 << 11) // Trap microcontroller range access -#define BIOS_RLS (1 << 7) // asserts SCI on bit set -#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set -#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# -#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# -#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic -#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit -#define EOS (1 << 1) // End of SMI (deassert SMI#) -#define GBL_SMI_EN (1 << 0) // SMI# generation at all? +#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic +#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic +#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS +#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) +#define MCSMI_EN (1 << 11) // Trap microcontroller range access +#define BIOS_RLS (1 << 7) // asserts SCI on bit set +#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set +#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# +#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# +#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic +#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit +#define EOS (1 << 1) // End of SMI (deassert SMI#) +#define GBL_SMI_EN (1 << 0) // SMI# generation at all? #define SMI_STS 0x34 #define ALT_GP_SMI_EN 0x38 #define ALT_GP_SMI_STS 0x3a @@ -504,7 +504,7 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define SS_CNT 0x50 #define C3_RES 0x54 #define TCO1_STS 0x64 -#define DMISCI_STS (1 << 9) +#define DMISCI_STS (1 << 9) #define TCO2_STS 0x66
/* @@ -549,16 +549,16 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
#define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ -#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ -#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ -#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ -#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ +#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ +#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ +#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ +#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ #define SPIBAR_HSFC 0x3806 /* SPI hardware sequence control */ -#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) -#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ -#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ -#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ -#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ +#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) +#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ +#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ +#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ +#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ #define SPIBAR_FADDR 0x3808 /* SPI flash address */ #define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */