Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48622 )
Change subject: WIP: soc/mediatek/mt8192: add apusys init flow ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48622/4/src/soc/mediatek/mt8192/apu... File src/soc/mediatek/mt8192/apusys.c:
https://review.coreboot.org/c/coreboot/+/48622/4/src/soc/mediatek/mt8192/apu... PS4, Line 11: : write32((void *)INFRA2APU_SRAM_PROT_EN, : read32((void *)INFRA2APU_SRAM_PROT_EN) & (~0xc0000000)); I'd encourage using SET32_BITFIELDS API for this, to provide better meaningful names
https://review.coreboot.org/c/coreboot/+/48622/4/src/soc/mediatek/mt8192/apu... PS4, Line 14: write32((void *)(APUSYS_MBOX + 0x0b0), 0x00010001); : write32((void *)(APUSYS_MBOX + 0x1b0), 0x00010001); : write32((void *)(APUSYS_MBOX + 0x2b0), 0x00010001); : write32((void *)(APUSYS_MBOX + 0x3b0), 0x00010001); : write32((void *)(APUSYS_MBOX + 0x4b0), 0x00010001); : write32((void *)(APUSYS_MBOX + 0x5b0), 0x00010001); : write32((void *)(APUSYS_MBOX + 0x6b0), 0x00010001); : write32((void *)(APUSYS_MBOX + 0x7b0), 0x00010001); : int i;
for (i = 0; i < 8; i++) { /* Explain what is this address pointing at */ SET32_BITFIELDS((void *)(APUSYS_MBOX + i * 0x100 + 0xb0), FIELD1_NAME, 1, FIELD2_NAME, 1); }