[coreboot-gerrit] Change in coreboot[master]: soc/intel/{apl,cnl,dnv,skl}: Skip ucode loading by FSP-T

[Subrata Banik (Code Review)]

Hello Patrick Rudolph, Vanny E, Lean Sheng Tan, Vincent Zimmer, build bot (Jenkins), David Guckian,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/37187

to look at the new patch set (#2).

Change subject: soc/intel/{apl,cnl,dnv,skl}: Skip ucode loading by FSP-T
......................................................................

soc/intel/{apl,cnl,dnv,skl}: Skip ucode loading by FSP-T

It is a requirement for Firmware to have Firmware Interface Table (FIT),
which contains pointers to each microcode update.
The microcode update is loaded for all logical processors before reset vector.

FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength are
input parameters to TempRamInit API.
If these values are 0, FSP will not attempt to update microcode.

Since Gen-4 all IA-SoC has FIT loading ucode even before cpu reset in place
hence skipping FSP-T loading ucode after CPU reset options.

Also removed unused kconfig CONFIG_CPU_MICROCODE_CBFS_LOC and
CONFIG_CPU_MICROCODE_CBFS_LEN

Change-Id: I3a406fa0e2e62e3363c2960e173dc5f5f5ca0455
Signed-off-by: Subrata Banik 
---
M src/cpu/Makefile.inc
M src/drivers/intel/fsp2_0/Kconfig
M src/soc/intel/apollolake/fspcar.c
M src/soc/intel/cannonlake/bootblock/bootblock.c
M src/soc/intel/denverton_ns/Kconfig
M src/soc/intel/denverton_ns/bootblock/bootblock.c
M src/soc/intel/skylake/fspcar.c
7 files changed, 50 insertions(+), 40 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/37187/2