Hello Chris Wang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/43408
to review the following change.
Change subject: [WIP] mb/google/zork: add dptc support ......................................................................
[WIP] mb/google/zork: add dptc support
add dptc support for different factory.
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Signed-off-by: Chris Wang chris.wang@amd.corp-partner.google.com Change-Id: Icae94103f254f8fdb84e6ee0f5404fb09fa97b2d --- M src/ec/google/chromeec/acpi/ec.asl M src/mainboard/google/zork/dsdt.asl A src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/dtpc.asl A src/mainboard/google/zork/variants/trembyle/include/variant/acpi/dptc.asl A src/soc/amd/picasso/acpi/dptc.asl M src/soc/amd/picasso/acpi/soc.asl A src/soc/amd/picasso/include/dptc.h 7 files changed, 145 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/43408/1
diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index f8d4bdf..993932a 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -10,7 +10,9 @@ #ifdef DPTF_ENABLE_CHARGER External (_SB.DPTF.TCHG, DeviceObj) #endif - +#ifdef DPTC_ENABLE +External(_SB.DPTC, MethodObj) +#endif
Device (EC0) { @@ -358,6 +360,9 @@ { Store ("EC: MKBP", Debug) Notify (CREC, 0x80) +#ifdef DPTC_ENABLE + _SB.DPTC(0x0) +#endif }
#ifdef EC_ENABLE_PD_MCU_DEVICE @@ -377,6 +382,9 @@ #ifdef EC_ENABLE_MULTIPLE_DPTF_PROFILES _SB.DPTF.TPET() #endif +#ifdef DPTC_ENABLE + _SB.DPTC(0x1) +#endif #ifdef EC_ENABLE_TBMC_DEVICE Notify (TBMC, 0x80) #endif diff --git a/src/mainboard/google/zork/dsdt.asl b/src/mainboard/google/zork/dsdt.asl index d256f66..e853c25 100644 --- a/src/mainboard/google/zork/dsdt.asl +++ b/src/mainboard/google/zork/dsdt.asl @@ -41,6 +41,8 @@ /* global utility methods expected within the _SB scope */ #include <arch/x86/acpi/globutil.asl>
+ #include <variant/acpi/dptc.asl> + /* Describe the SOC */ #include <soc.asl>
diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/dtpc.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/dtpc.asl new file mode 100644 index 0000000..b421ae3 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/dtpc.asl @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define SUSTAINED_POWER_LIMIT_MW_0 25000 +#define SLOW_PPT_LIMIT_MW_0 30000 + +#define SUSTAINED_POWER_LIMIT_MW_1 16000 +#define SLOW_PPT_LIMIT_MW_1 20000 + diff --git a/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/dptc.asl b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/dptc.asl new file mode 100644 index 0000000..d43a9c6 --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/dptc.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptc.asl> diff --git a/src/soc/amd/picasso/acpi/dptc.asl b/src/soc/amd/picasso/acpi/dptc.asl new file mode 100644 index 0000000..9bd9779 --- /dev/null +++ b/src/soc/amd/picasso/acpi/dptc.asl @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #define DPTC_CTDP 0x0 + #define DPTC_STAPM_TIME_CONSTANT 0x1 + #define DPTC_SKIN_CONTROL_SCALAR 0x2 + #define DPTC_THERMAL_CONTROL_LIMIT 0x3 + #define DPTC_PACKAGE_POWER_LIMIT 0x4 + #define DPTC_SUSTAINED_POWER_LIMIT 0x5 + #define DPTC_FAST_PPT_LIMIT 0x6 + #define DPTC_SLOW_PPT_LIMIT 0x7 + #define DPTC_SLOW_PPT_TIME_CONSTANT 0x8 + #define DPTC_PROCHOT_L 0x9 + #define DPTC_SYS_TEMP_TRACKING 0xa + #define DPTC_VRM_CURRENT_LIMIT 0xb + #define DPTC_VRM_MAXIMUM_CURRENT_LIMIT 0xc + #define DPTC_VRM_LOW_POWER_THRESHOLD 0xd + #define DPTC_VRM_SOC_CURRENT_LIMIT 0xe + #define DPTC_VRM_SOC_LOW_POWER_THRESHOLD 0xf + #define DPTC_DGPU_CONTROL 0x10 +#define DPTC_PROFILE_0 0x0 +#define DPTC_PROFILE_1 0x1 +External(_SB.ALIB, MethodObj) +Name(DPTI, Buffer(0x07){}) +CreateWordField(DPTI, Zero, SSZE) +CreateByteField(DPTI, 0x02,MSID) +CreateDwordField(DPTI,0x03,DECI) +/* System Bus */ +Method(DPTC, 1, Serialized) +{ + Method(POF0, 0, Serialized) { + Store(0x07, SSZE) + Store(DPTC_SUSTAINED_POWER_LIMIT, MSID) + Store(SUSTAINED_POWER_LIMIT_MW_0, DECI) + ALIB(0xC, DPTI) //for PL1:Sustained power limit + Store(0x07, SSZE) + Store(DPTC_SLOW_PPT_LIMIT, MSID) + Store(SLOW_PPT_LIMIT_MW_0, DECI) + ALIB(0xC, DPTI) //for PL2:Slow PPT limit + } + Method(POF1, 0, Serialized) { + Store(0x07, SSZE) + Store(DPTC_SUSTAINED_POWER_LIMIT, MSID) + Store(SUSTAINED_POWER_LIMIT_MW_1, DECI) + ALIB(0xC, DPTI) //for PL1:Sustained power limit + Store(0x07, SSZE) + Store(DPTC_SLOW_PPT_LIMIT, MSID) + Store(SLOW_PPT_LIMIT_MW_1, DECI) + ALIB(0xC, DPTI) //for PL2:Slow PPT limit + } + Switch (ToInteger(Arg0)) + { + Case (DPTC_PROFILE_0) { + POF0() + } + Case (DPTC_PROFILE_1) { + POF1() + } + } +} diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl index b3b036e..909b985 100644 --- a/src/soc/amd/picasso/acpi/soc.asl +++ b/src/soc/amd/picasso/acpi/soc.asl @@ -17,5 +17,7 @@ /* Describe the devices in the Southbridge */ #include "sb_fch.asl"
+#include "dptc.asl" + /* Add GPIO library */ #include <soc/amd/common/acpi/gpio_bank_lib.asl> diff --git a/src/soc/amd/picasso/include/dptc.h b/src/soc/amd/picasso/include/dptc.h new file mode 100644 index 0000000..c4f723b --- /dev/null +++ b/src/soc/amd/picasso/include/dptc.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #define DPTC_CTDP 0x0 + #define DPTC_STAPM_TIME_CONSTANT 0x1 + #define DPTC_SKIN_CONTROL_SCALAR 0x2 + #define DPTC_THERMAL_CONTROL_LIMIT 0x3 + #define DPTC_PACKAGE_POWER_LIMIT 0x4 + #define DPTC_SUSTAINED_POWER_LIMIT 0x5 + #define DPTC_FAST_PPT_LIMIT 0x6 + #define DPTC_SLOW_PPT_LIMIT 0x7 + #define DPTC_SLOW_PPT_TIME_CONSTANT 0x8 + #define DPTC_SYS_TEMP_TRACKING 0xA + #define DPTC_VRM_CURRENT_LIMIT 0xb + #define DPTC_VRM_MAXIMUM_CURRENT_LIMIT 0xc + #define DPTC_VRM_LOW_POWER_THRESHOLD 0xd + #define DPTC_VRM_SOC_CURRENT_LIMIT 0xe + #define DPTC_VRM_SOC_LOW_POWER_THRESHOLD 0xf + #define DPTC_DGPU_CONTROL 0x10